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Searched refs:MCFSIM_ICR1 (Results 1 – 25 of 161) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
131 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
131 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
131 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
131 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
131 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */

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