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Searched refs:MCFSIM_ICR3 (Results 1 – 25 of 91) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c62 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
63 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
64 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
65 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
66 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
67 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
68 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
69 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
168 writel(0x88888888, MCFSIM_ICR3); in init_IRQ()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c62 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
63 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
64 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
65 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
66 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
67 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
68 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
69 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
168 writel(0x88888888, MCFSIM_ICR3); in init_IRQ()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/m68k/coldfire/
H A Dintc-5272.c62 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
63 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
64 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
65 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
66 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
67 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
68 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
69 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
168 writel(0x88888888, MCFSIM_ICR3); in init_IRQ()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h67 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
133 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h67 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
133 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h67 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
133 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h67 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
133 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/include/asm/
H A Dm5249.h67 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
133 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/m68k/include/asm/
H A Dm5249.h50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ macro
116 #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */

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