/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/ |
H A D | davicom.c | 89 #define MDCLKH 0x10000 macro 302 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/net/ipxe/ipxe-2265a65/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/ |
H A D | davicom.c | 86 #define MDCLKH 0x10000 macro 285 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/ |
H A D | uli526x.c | 74 #define MDCLKH 0x10000 macro 944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/net/ |
H A D | uli526x.c | 78 #define MDCLKH 0x10000 macro 942 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/ |
H A D | uli526x.c | 74 #define MDCLKH 0x10000 macro 944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/net/ |
H A D | uli526x.c | 78 #define MDCLKH 0x10000 macro 942 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/net/ |
H A D | uli526x.c | 78 #define MDCLKH 0x10000 macro 942 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/ |
H A D | uli526x.c | 74 #define MDCLKH 0x10000 macro 944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/net/ |
H A D | uli526x.c | 78 #define MDCLKH 0x10000 macro 942 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/ |
H A D | uli526x.c | 75 #define MDCLKH 0x10000 macro 945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
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