| /dports/emulators/z80pack/z80pack-1.37/imsaisim/srcsim/ |
| H A D | memory.h | 32 #define MEM_RW 0 /* memory is readable and writeable */ macro
63 #define MEM_RELEASE(page) p_tab[(page)] = (ram_size > (page)) ? MEM_RW : MEM_NONE
65 #define MEM_ROM_BANK_ON(page) p_tab[(page)] = (ram_size > (page)) ? MEM_RW : MEM_RO
67 #define MEM_RESERVE_RAM(page) p_tab[(page)] = MEM_RW
77 if (p_tab[addr >> 10] == MEM_RW) in memwrt()
173 if (p_tab[addr >> 10] == MEM_RW) in dma_write()
210 if (p_tab[addr >> 10] == MEM_RW) in fp_write()
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| /dports/net/tigervnc-server/tigervnc-1.12.0/unix/xserver/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| H A D | helper_mem.c | 297 segments[0] = MEM_RW(pInt, (0x10 << 2) + 2); in xf86int10GetBiosSegment()
298 segments[1] = MEM_RW(pInt, (0x42 << 2) + 2); in xf86int10GetBiosSegment()
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| /dports/x11-servers/xorg-dmx/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xwayland-devel/xorg-xserver-xorg-server-21.0.99.1-177-g9e5a37961/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| H A D | helper_mem.c | 297 segments[0] = MEM_RW(pInt, (0x10 << 2) + 2); in xf86int10GetBiosSegment()
298 segments[1] = MEM_RW(pInt, (0x42 << 2) + 2); in xf86int10GetBiosSegment()
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| /dports/x11-servers/xorg-vfbserver/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xwayland/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xorg-server/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xephyr/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xorg-nestserver/xorg-server-1.20.13/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/x11-servers/xarcan/xarcan-0.6.0/hw/xfree86/int10/ |
| H A D | xf86int10.c | 125 int1d = MEM_RW(pInt, 0x1d << 2); in int42_handler()
143 tmp = MEM_RW(pInt, (mode & 0x06) + int1d + 0x40); in int42_handler()
194 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
223 offset = (X86_DH * MEM_RW(pInt, 0x044A)) + X86_DL; in int42_handler()
224 offset += MEM_RW(pInt, 0x044E) << 1; in int42_handler()
226 ioport = MEM_RW(pInt, 0x0463); in int42_handler()
277 unsigned int ioport = MEM_RW(pInt, 0x0463); in int42_handler()
283 start = X86_AL * MEM_RW(pInt, 0x044C); in int42_handler()
296 start += (y * MEM_RW(pInt, 0x044A)) + x; in int42_handler()
427 unsigned int ioport = MEM_RW(pInt, 0x0463) + 5; in int42_handler()
[all …]
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| H A D | helper_exec.c | 108 return MEM_RW(pInt, num << 2) + (MEM_RW(pInt, (num << 2) + 2) << 4); in getIntVect()
125 if (MEM_RW(pInt, (num << 2) + 2) == (SYS_BIOS >> 4)) { /* SYS_BIOS_SEG ? */ in run_bios_int()
157 X86_CS = MEM_RW(pInt, (num << 2) + 2); in run_bios_int()
158 X86_IP = MEM_RW(pInt, num << 2); in run_bios_int()
302 x_outw(port, MEM_RW(pInt, dst)); in port_rep_outw()
722 *(base + i) = MEM_RW(pInt, i); in SetResetBIOSVars()
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| /dports/emulators/z80pack/z80pack-1.37/altairsim/srcsim/ |
| H A D | memory.h | 27 #define MEM_RW 0 /* memory is readable and writeable */ macro
58 if (p_tab[addr >> 8] == MEM_RW) { in memwrt()
116 if (p_tab[addr >> 8] == MEM_RW) in dma_write()
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| /dports/devel/gdb/gdb-11.1/gdb/ |
| H A D | memattr.h | 26 MEM_RW, /* read/write */ enumerator
65 enum mem_access_mode mode = MEM_RW;
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| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | memattr.c | 33 MEM_RW, /* mode */
159 attrib.mode = MEM_RW; in mem_command()
281 case MEM_RW: in mem_info_command()
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| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | memattr.c | 33 MEM_RW, /* mode */
159 attrib.mode = MEM_RW; in mem_command()
281 case MEM_RW: in mem_info_command()
|