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Searched refs:MINREG (Results 1 – 19 of 19) sorted by relevance

/dports/lang/go-devel/go-dragonfly-amd64-bootstrap/src/cmd/internal/obj/wasm/
H A Dwasmobj.go90 registerNames[reg-MINREG] = name
95 return registerNames[r-MINREG]
815 REG_SP - MINREG: {true, 0},
816 REG_CTXT - MINREG: {true, 1},
817 REG_g - MINREG: {true, 2},
818 REG_RET0 - MINREG: {true, 3},
819 REG_RET1 - MINREG: {true, 4},
864 if regUsed[reg-MINREG] {
906 v := regVars[reg-MINREG]
928 v := regVars[reg-MINREG]
[all …]
H A Da.out.go327 MINREG = REG_SP const
/dports/lang/go-devel/go-becaeea1199b875bc24800fa88f2f4fea119bf78/src/cmd/internal/obj/wasm/
H A Dwasmobj.go90 registerNames[reg-MINREG] = name
95 return registerNames[r-MINREG]
827 REG_SP - MINREG: {true, 0},
828 REG_CTXT - MINREG: {true, 1},
829 REG_g - MINREG: {true, 2},
830 REG_RET0 - MINREG: {true, 3},
831 REG_RET1 - MINREG: {true, 4},
876 if regUsed[reg-MINREG] {
918 v := regVars[reg-MINREG]
940 v := regVars[reg-MINREG]
[all …]
H A Da.out.go327 MINREG = REG_SP const
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …gpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …gpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …u=tahiti -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,SI-MINREG %s
3 …cpu=fiji -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit2.ll1 …-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
6 ; SI-MINREG: NumSgprs: {{[1-9]$}}
7 ; SI-MINREG: NumVgprs: {{[1-9]$}}