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Searched refs:MISCCFG_GPE0_DW1_SHIFT (Results 1 – 25 of 57) sorted by relevance

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/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
467 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12 macro
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; in pinctrl_route_gpe()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/pinctrl/intel/
H A Dpinctrl.c42 #define MISCCFG_GPE0_DW1_SHIFT 12
43 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
479 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;

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