| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/ |
| H A D | stm32g4xx_ll_tim.c | 829 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
835 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
987 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1249 MODIFY_REG(TIMx->CCMR1, in IC1Config()
1254 MODIFY_REG(TIMx->CCER, in IC1Config()
1282 MODIFY_REG(TIMx->CCMR1, in IC2Config()
1287 MODIFY_REG(TIMx->CCER, in IC2Config()
1315 MODIFY_REG(TIMx->CCMR2, in IC3Config()
1320 MODIFY_REG(TIMx->CCER, in IC3Config()
1348 MODIFY_REG(TIMx->CCMR2, in IC4Config()
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| H A D | stm32g4xx_hal_flash_ramfunc.c | 172 …MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_S… in HAL_FLASHEx_OB_DBankConfig()
180 …MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_S… in HAL_FLASHEx_OB_DBankConfig()
188 …MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_S… in HAL_FLASHEx_OB_DBankConfig()
196 …MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_S… in HAL_FLASHEx_OB_DBankConfig()
200 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); in HAL_FLASHEx_OB_DBankConfig()
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| H A D | stm32g4xx_hal_uart_ex.c | 229 MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); in HAL_RS485Ex_Init()
234 MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); in HAL_RS485Ex_Init()
372 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); in HAL_MultiProcessorEx_AddressLength_Set()
412 MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); in HAL_UARTEx_StopModeWakeUpSourceConfig()
593 MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); in HAL_UARTEx_SetTxFifoThreshold()
642 MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); in HAL_UARTEx_SetRxFifoThreshold()
681 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); in UARTEx_Wakeup_AddressConfig()
684 …MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADD… in UARTEx_Wakeup_AddressConfig()
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| H A D | stm32g4xx_hal_dac_ex.c | 406 …MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WA… in HAL_DACEx_TriangleWaveGenerate()
458 …MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WA… in HAL_DACEx_NoiseWaveGenerate()
512 MODIFY_REG(hdac->Instance->STR1, in HAL_DACEx_SawtoothWaveGenerate()
521 MODIFY_REG(hdac->Instance->STR2, in HAL_DACEx_SawtoothWaveGenerate()
529 …MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1) << (Channel & 0x10UL), (uint32_t)(DAC_CR_WAVE1_1 | D… in HAL_DACEx_SawtoothWaveGenerate()
817 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); in HAL_DACEx_SelfCalibrate()
844 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
866 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
877 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
888 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); in HAL_DACEx_SelfCalibrate()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/ |
| H A D | stm32h7xx_ll_tim.c | 841 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
847 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
999 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1252 MODIFY_REG(TIMx->CCMR1, in IC1Config()
1257 MODIFY_REG(TIMx->CCER, in IC1Config()
1285 MODIFY_REG(TIMx->CCMR1, in IC2Config()
1290 MODIFY_REG(TIMx->CCER, in IC2Config()
1318 MODIFY_REG(TIMx->CCMR2, in IC3Config()
1323 MODIFY_REG(TIMx->CCER, in IC3Config()
1351 MODIFY_REG(TIMx->CCMR2, in IC4Config()
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| H A D | stm32h7xx_hal.c | 518 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); in HAL_SYSCFG_VREFBUF_VoltageScalingConfig()
534 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); in HAL_SYSCFG_VREFBUF_HighImpedanceConfig()
546 MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); in HAL_SYSCFG_VREFBUF_TrimmingConfig()
597 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); in HAL_SYSCFG_ETHInterfaceSelect()
628 MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); in HAL_SYSCFG_AnalogSwitchConfig()
685 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16)); in HAL_SYSCFG_CM7BootAddConfig()
687 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); in HAL_SYSCFG_CM7BootAddConfig()
712 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos)); in HAL_SYSCFG_CM4BootAddConfig()
718 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16)); in HAL_SYSCFG_CM4BootAddConfig()
820 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode)); in HAL_SYSCFG_CompensationCodeSelect()
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| H A D | stm32h7xx_hal_dac_ex.c | 125 …MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WA… in HAL_DACEx_TriangleWaveGenerate()
174 …MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WA… in HAL_DACEx_NoiseWaveGenerate()
347 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); in HAL_DACEx_SelfCalibrate()
373 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
396 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
407 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
418 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); in HAL_DACEx_SelfCalibrate()
464 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Chan… in HAL_DACEx_SetUserTrimming()
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| H A D | stm32h7xx_hal_uart_ex.c | 229 MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); in HAL_RS485Ex_Init()
234 MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); in HAL_RS485Ex_Init()
369 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); in HAL_MultiProcessorEx_AddressLength_Set()
409 MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); in HAL_UARTEx_StopModeWakeUpSourceConfig()
590 MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); in HAL_UARTEx_SetTxFifoThreshold()
639 MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); in HAL_UARTEx_SetRxFifoThreshold()
678 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); in UARTEx_Wakeup_AddressConfig()
681 …MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADD… in UARTEx_Wakeup_AddressConfig()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/ |
| H A D | stm32h7xx_hal_rcc_ex.h | 1368 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
1379 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
1476 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
1487 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
1501 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
1525 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
1570 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
1595 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
1620 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
1645 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
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| H A D | stm32h7xx_ll_dac.h | 564 MODIFY_REG(DACx->CR, in LL_DAC_SetMode()
604 MODIFY_REG(DACx->CCR, in LL_DAC_SetTrimmingValue()
661 MODIFY_REG(DACx->CR, in LL_DAC_SetTriggerSource()
718 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveAutoGeneration()
775 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveNoiseLFSR()
841 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveTriangleAmplitude()
922 MODIFY_REG(DACx->MCR, in LL_DAC_ConfigOutput()
1095 MODIFY_REG(*preg, in LL_DAC_SetSampleAndHoldSampleTime()
1454 MODIFY_REG(*preg, in LL_DAC_ConvertData12RightAligned()
1476 MODIFY_REG(*preg, in LL_DAC_ConvertData12LeftAligned()
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| H A D | stm32h7xx_ll_rcc.h | 1205 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); in LL_RCC_HSI_SetDivider()
1268 MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U); in LL_RCC_HSI_SetCalibTrimming()
1685 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
1770 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
1797 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); in LL_RCC_SetSysWakeUpClkSource()
1822 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); in LL_RCC_SetKerWakeUpClkSource()
1874 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
3055 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); in LL_RCC_SetRTCClockSource()
3193 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); in LL_RCC_SetRTC_HSEPrescaler()
3287 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); in LL_RCC_SetTIMPrescaler()
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| H A D | stm32h7xx_ll_pwr.h | 314 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); in LL_PWR_SetRegulModeDS()
375 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
467 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
525 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); in LL_PWR_SetAVDLevel()
733 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
818 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); in LL_PWR_CPU_SetD1PowerMode()
872 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); in LL_PWR_CPU_SetD2PowerMode()
926 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); in LL_PWR_CPU_SetD3PowerMode()
1276 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullNone()
1300 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullUp()
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| H A D | stm32h7xx_ll_usart.h | 956 MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); in LL_USART_SetWakeUpMethod()
985 MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); in LL_USART_SetDataWidth()
1108 MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); in LL_USART_SetClockPhase()
1288 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); in LL_USART_SetStopBitsLength()
1337 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); in LL_USART_ConfigCharacter()
1351 MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); in LL_USART_SetTXRXSwap()
1814 MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); in LL_USART_SetWKUPType()
1952 MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); in LL_USART_SetRxTimeout()
2049 MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); in LL_USART_SetIrdaPowerMode()
2428 MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); in LL_USART_SetLINBrkDetectionLen()
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| H A D | stm32h7xx_ll_adc.h | 2799 MODIFY_REG(*preg, in LL_ADC_SetOffset()
3413 MODIFY_REG(*preg, in LL_ADC_REG_SetSequencerRanks()
4460 MODIFY_REG(*preg, in LL_ADC_SetChannelSamplingTime()
4804 MODIFY_REG(*preg, in LL_ADC_SetAnalogWDMonitChannels()
5575 MODIFY_REG(ADCx->CR, in LL_ADC_EnableDeepPowerDown()
5631 MODIFY_REG(ADCx->CR, in LL_ADC_EnableInternalRegulator()
5682 MODIFY_REG(ADCx->CR, in LL_ADC_Enable()
5702 MODIFY_REG(ADCx->CR, in LL_ADC_Disable()
5770 MODIFY_REG(ADCx->CR, in LL_ADC_StartCalibration()
5817 MODIFY_REG(ADCx->CR, in LL_ADC_REG_StartConversion()
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| H A D | stm32h7xx_ll_lpuart.h | 795 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); in LL_LPUART_SetWakeUpMethod()
823 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); in LL_LPUART_SetDataWidth()
931 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); in LL_LPUART_SetStopBitsLength()
975 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); in LL_LPUART_ConfigCharacter()
989 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); in LL_LPUART_SetTXRXSwap()
1016 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); in LL_LPUART_SetRXPinLevel()
1043 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); in LL_LPUART_SetTXPinLevel()
1073 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); in LL_LPUART_SetBinaryDataLogic()
1102 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); in LL_LPUART_SetTransferBitOrder()
1299 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); in LL_LPUART_SetWKUPType()
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/ |
| H A D | stm32g4xx_ll_fmac.h | 169 MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark); in LL_FMAC_SetX1FullWatermark()
221 MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos); in LL_FMAC_SetX1Base()
269 MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos); in LL_FMAC_SetX2Base()
296 MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark); in LL_FMAC_SetYEmptyWatermark()
348 MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos); in LL_FMAC_SetYBase()
409 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function); in LL_FMAC_SetFunction()
438 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos); in LL_FMAC_SetParamR()
462 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos); in LL_FMAC_SetParamQ()
486 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); in LL_FMAC_SetParamP()
957 MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE, in LL_FMAC_ConfigX2()
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| H A D | stm32g4xx_ll_dac.h | 668 MODIFY_REG(DACx->CR, in LL_DAC_SetMode()
790 MODIFY_REG(DACx->CR, in LL_DAC_SetTriggerSource()
867 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveAutoGeneration()
931 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveNoiseLFSR()
1067 MODIFY_REG(*preg, in LL_DAC_SetWaveSawtoothPolarity()
1118 MODIFY_REG(*preg, in LL_DAC_SetWaveSawtoothResetData()
1170 MODIFY_REG(*preg, in LL_DAC_SetWaveSawtoothStepData()
1638 MODIFY_REG(*preg, in LL_DAC_SetSampleAndHoldSampleTime()
2216 MODIFY_REG(*preg, in LL_DAC_ConvertData12RightAligned()
2241 MODIFY_REG(*preg, in LL_DAC_ConvertData12LeftAligned()
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| H A D | stm32g4xx_hal_rcc_ex.h | 653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
678 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
723 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
744 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
764 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
786 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
833 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
858 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
906 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
928 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
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| H A D | stm32g4xx_ll_rcc.h | 1175 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
1310 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); in LL_RCC_LSCO_SetSource()
1344 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
1377 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
1393 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); in LL_RCC_SetAPB1Prescaler()
1409 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); in LL_RCC_SetAPB2Prescaler()
1621 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); in LL_RCC_SetSAIClockSource()
1636 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource); in LL_RCC_SetI2SClockSource()
1665 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource); in LL_RCC_SetRNGClockSource()
1713 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source); in LL_RCC_SetQUADSPIClockSource()
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| H A D | stm32g4xx_ll_usart.h | 956 MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); in LL_USART_SetWakeUpMethod()
985 MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); in LL_USART_SetDataWidth()
1108 MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); in LL_USART_SetClockPhase()
1288 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); in LL_USART_SetStopBitsLength()
1337 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); in LL_USART_ConfigCharacter()
1351 MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); in LL_USART_SetTXRXSwap()
1814 MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); in LL_USART_SetWKUPType()
1952 MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); in LL_USART_SetRxTimeout()
2049 MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); in LL_USART_SetIrdaPowerMode()
2428 MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); in LL_USART_SetLINBrkDetectionLen()
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| H A D | stm32g4xx_ll_spi.h | 400 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
429 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); in LL_SPI_SetStandard()
458 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); in LL_SPI_SetClockPhase()
487 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); in LL_SPI_SetClockPolarity()
521 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); in LL_SPI_SetBaudRatePrescaler()
555 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); in LL_SPI_SetTransferBitOrder()
630 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); in LL_SPI_SetDataWidth()
668 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); in LL_SPI_SetRxFIFOThreshold()
740 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); in LL_SPI_SetCRCWidth()
835 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); in LL_SPI_SetNSSMode()
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| /dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_rtc.h | 856 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
972 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1140 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1173 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1249 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1447 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), in LL_RTC_DATE_SetYear()
1531 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), in LL_RTC_DATE_SetMonth()
1576 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), in LL_RTC_DATE_SetDay()
2471 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); in LL_RTC_TS_SetActiveEdge()
2975 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); in LL_RTC_WAKEUP_SetAutoReload()
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| /dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_rtc.h | 856 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
972 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1140 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1173 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1249 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1447 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), in LL_RTC_DATE_SetYear()
1531 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), in LL_RTC_DATE_SetMonth()
1576 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), in LL_RTC_DATE_SetDay()
2471 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); in LL_RTC_TS_SetActiveEdge()
2975 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); in LL_RTC_WAKEUP_SetAutoReload()
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| /dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_rtc.h | 856 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
972 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1140 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1173 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1249 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1447 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), in LL_RTC_DATE_SetYear()
1531 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), in LL_RTC_DATE_SetMonth()
1576 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), in LL_RTC_DATE_SetDay()
2471 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); in LL_RTC_TS_SetActiveEdge()
2975 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); in LL_RTC_WAKEUP_SetAutoReload()
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| /dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
| H A D | stm32l1xx_ll_rtc.h | 856 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
972 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1140 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1173 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1249 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1447 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), in LL_RTC_DATE_SetYear()
1531 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), in LL_RTC_DATE_SetMonth()
1576 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), in LL_RTC_DATE_SetDay()
2471 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); in LL_RTC_TS_SetActiveEdge()
2975 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); in LL_RTC_WAKEUP_SetAutoReload()
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