| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 125 #define MSCC_DW8051_CNTL_STATUS 0 macro
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
374 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
591 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
637 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 125 #define MSCC_DW8051_CNTL_STATUS 0 macro
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
374 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
591 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
637 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 125 #define MSCC_DW8051_CNTL_STATUS 0 macro
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
374 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
591 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
637 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 125 #define MSCC_DW8051_CNTL_STATUS 0 macro
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
374 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
591 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
637 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
343 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
376 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
378 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
593 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
639 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/net/phy/ |
| H A D | mscc.c | 125 #define MSCC_DW8051_CNTL_STATUS 0 macro
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
374 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
591 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
637 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/net/phy/ |
| H A D | mscc.c | 127 #define MSCC_DW8051_CNTL_STATUS 0 macro
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
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