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Searched refs:MSR_UMS (Results 1 – 25 of 41) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/microblaze/kernel/
H A Dprocess.c82 childregs->msr |= MSR_UMS; in copy_thread()
101 ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */ in copy_thread()
127 regs->msr |= MSR_UMS; in start_thread()
H A Dentry.S78 msrset r0, MSR_UMS
83 msrclr r0, MSR_UMS
88 msrclr r0, MSR_UMS
92 msrclr r0, MSR_VMS | MSR_UMS
134 andni r11, r11, MSR_UMS
141 andni r11, r11, MSR_UMS
147 andni r11, r11, MSR_UMS
153 andni r11, r11, (MSR_VMS|MSR_UMS)
259 andi r1, r1, MSR_UMS; \
660 andi r1, r1, MSR_UMS
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/microblaze/kernel/
H A Dprocess.c82 childregs->msr |= MSR_UMS; in copy_thread()
101 ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */ in copy_thread()
127 regs->msr |= MSR_UMS; in start_thread()
H A Dentry.S78 msrset r0, MSR_UMS
83 msrclr r0, MSR_UMS
88 msrclr r0, MSR_UMS
92 msrclr r0, MSR_VMS | MSR_UMS
134 andni r11, r11, MSR_UMS
141 andni r11, r11, MSR_UMS
147 andni r11, r11, MSR_UMS
153 andni r11, r11, (MSR_VMS|MSR_UMS)
259 andi r1, r1, MSR_UMS; \
660 andi r1, r1, MSR_UMS
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/microblaze/kernel/
H A Dprocess.c82 childregs->msr |= MSR_UMS; in copy_thread()
101 ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */ in copy_thread()
127 regs->msr |= MSR_UMS; in start_thread()
H A Dentry.S78 msrset r0, MSR_UMS
83 msrclr r0, MSR_UMS
88 msrclr r0, MSR_UMS
92 msrclr r0, MSR_VMS | MSR_UMS
134 andni r11, r11, MSR_UMS
141 andni r11, r11, MSR_UMS
147 andni r11, r11, MSR_UMS
153 andni r11, r11, (MSR_VMS|MSR_UMS)
259 andi r1, r1, MSR_UMS; \
660 andi r1, r1, MSR_UMS
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/target/microblaze/
H A Dhelper.c140 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
183 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
231 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ in mb_cpu_do_interrupt()
250 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/microblaze/
H A Dhelper.c140 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
183 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
231 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ in mb_cpu_do_interrupt()
250 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu42/qemu-4.2.1/target/microblaze/
H A Dhelper.c140 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
183 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
231 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ in mb_cpu_do_interrupt()
250 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/microblaze/
H A Dhelper.c139 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
182 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
230 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ in mb_cpu_do_interrupt()
249 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dcpu.h77 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/microblaze/
H A Dhelper.c140 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
183 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
231 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \ in mb_cpu_do_interrupt()
250 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/microblaze/include/asm/
H A Dregisters.h32 # define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/microblaze/include/asm/
H A Dregisters.h32 # define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/microblaze/include/asm/
H A Dregisters.h32 # define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu5/qemu-5.2.0/target/microblaze/
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
H A Dhelper.c212 msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/microblaze/
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
H A Dhelper.c217 msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
/dports/emulators/qemu/qemu-6.2.0/target/microblaze/
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro
/dports/emulators/qemu60/qemu-6.0.0/target/microblaze/
H A Dcpu.h71 #define MSR_UMS (1<<12) /* User Mode Save */ macro

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