1 /* 2 * Copyright (c) 2015-2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mos_os_trace_event.h 24 //! \brief MOS trace event header file. 25 //! \details only contain trace event id and type definition, which will keep 26 //! growing. 27 //! 28 29 #ifndef __MOS_OS_TRACE_H__ 30 #define __MOS_OS_TRACE_H__ 31 32 typedef enum _MEDIA_EVENT 33 { 34 UNDEFINED_EVENT = 0, //! reserved id, should not used in driver 35 EVENT_RESOURCE_ALLOCATE, //! event for MOS resource allocate 36 EVENT_RESOURCE_FREE, //! event for MOS resource free 37 EVENT_RESOURCE_REGISTER, //! event for register MOS resource to gpu command 38 EVENT_RESOURCE_PATCH, //! event for patch MOS resource 39 EVENT_PPED_HUC, //! event for PPED HuC path 40 EVENT_PPED_FW, //! event for PPED FW path 41 EVENT_PPED_AUDIO, //! event for PPED audio path 42 EVENT_BLT_ENC, //! event for blt enc mode 43 EVENT_BLT_DEC, //! event for blt dec mode 44 EVENT_PPED_HW_CAPS, //! event for PPED HW capability 45 EVENT_MOS_MESSAGE, //! event for MOS debug message 46 EVENT_CODEC_NV12ToP010, //! event for NV12 to P010 in codechal 47 EVENT_CODEC_CENC, //! event for CENC Decode 48 EVENT_CODEC_DECODE_DDI, //! event for Decoder decode DDI level 49 EVENT_CODEC_DECODE, //! event for Decoder decode 50 EVENT_CODEC_ENCODE_DDI, //! event for Decoder encode DDI level 51 EVENT_ENCODER_CREATE, //! event for encoder create 52 EVENT_ENCODER_DESTROY, //! event for encoder destory. 53 EVENT_CODECHAL_CREATE, //! event for codechal create. 54 EVENT_CODECHAL_EXECUTE, //! event for codechal execute. 55 EVENT_CODECHAL_DESTROY, //! event for codechal destory. 56 EVENT_MHW_PROLOG, //! event for MHW GPU cmd prolog. 57 EVENT_MHW_EPILOG, //! event for MHW GPU cmd epilog. 58 EVENT_KEYEXCHANGE_WV, //! event for WV key exchange 59 EVENT_TEST1, //! event for immediate event trace usage in debug. 60 EVENT_TEST2, //! avoid build manifest for temp event. 61 EVENT_TEST3, //! pre allocate 3 events. 62 EVENT_CP_CREATE, //! event for cp session create 63 EVENT_CP_DESTROY, //! event for cp session destroy 64 EVENT_HECI_IOMSG, //! event for heci IO message send receive 65 EVENT_CP_CHECK_SESSION_STATUS, //! event for cp session status check 66 EVENT_CP_RESOURCR_SESSION, //! event for cp resource session create 67 EVENT_PREPARE_RESOURCES, //! event for prepare resource 68 EVENT_DDI_CODEC_CREATE, //! event for ddi tracking - codec create 69 EVENT_DDI_CODEC_DESTROY, //! event for ddi tracking - codec destroy 70 EVENT_DDI_CODEC_VIEW, //! event for ddi tracking - codec view 71 EVENT_DDI_VP_CREATE, //! event for ddi tracking - vp create 72 EVENT_DDI_VP_DESTROY, //! event for ddi tracking - vp destroy 73 EVENT_DDI_VP_VIEW, //! event for ddi tracking - vp view 74 EVENT_DDI_VP_BLT, //! event for ddi tracking - vp blt 75 EVENT_DDI_VP_BLT_SETSTATE, //! event for ddi tracking - vp blt stream state 76 EVENT_DDI_VPHAL_REPORT, //! event for ddi tracking - vp hal report 77 EVENT_DDI_VP_BLT_HINTS, //! event for ddi tracking - vp blt hints 78 EVENT_CP_CERT_COUNT, //! event for number of certs 79 EVENT_CP_CERT_NOT_FOUND, //! event for certificate not found 80 EVENT_DDI_VIDEOVIEW_CLEAR, //! event for ddi tracking - ClearVideoView 81 EVENT_DDE_FUNCTION, //! event for function enter/exit 82 EVENT_DDE_QUERY_HDCP_INTERFACE, //! event for cp ddi 83 EVENT_DDE_CB_REPORT_AUTH_RESULT, 84 EVENT_DDE_ESCAPE, 85 EVENT_DDE_AKE_INIT, //! event for HDCP 2 messages 86 EVENT_DDE_AKE_SEND_CERT, 87 EVENT_DDE_AKE_NOSTORED_KM, 88 EVENT_DDE_AKE_STORED_KM, 89 EVENT_DDE_AKE_SEND_RRX, 90 EVENT_DDE_AKE_SEND_HRPIME, 91 EVENT_DDE_SKE_SEND_EKS, 92 EVENT_DDE_AKE_TRANSMITTER_INFO, 93 EVENT_DDE_AKE_RECEIVER_INFO, 94 EVENT_DDE_REPAUTH_SEND_RXIDLIST, 95 EVENT_DDE_REPAUTH_SEND_ACK, 96 EVENT_DDE_REPAUTH_STREAM_MANAGE, 97 EVENT_DDE_REPAUTH_STREAM_READY, 98 EVENT_DDE_RECEIVER_AUTHSTATUS, 99 EVENT_DDE_CREATE_HDCP_CONTEXT, 100 EVENT_DDE_DESTROY_HDCP_CONTEXT, 101 EVENT_DDE_RECEIVE_DATA, 102 EVENT_DDE_CB_REPORT_ENCRYPTION_STATUS, 103 EVENT_DDE_CB_REPORT_LINK_STATUS, 104 EVENT_DDE_CB_SEND_DATA, 105 EVENT_DDE_MESSAGE, //! event for debug message 106 EVENT_OCA_ERROR, //! event for OCA error. 107 EVENT_DATA_DUMP, //! event for debug data dump 108 EVENT_HECI_OBJ, //! event for heci duplicate handle 109 EVENT_PLAT_INFO, //! event for static platform info 110 EVENT_DATA_DICTIONARY, //! event for data dictionary (name:value pair) 111 EVENT_MEDIA_COPY, //! event for media decompresss/copy/blt 112 EVENT_MOS_BATCH_SUBMIT, //! event for batch buffer submission 113 EVENT_VA_PICTURE, //! event for VA begin/render/end picture 114 EVENT_VA_SYNC, //! event for VA sync surface/buffer 115 EVENT_VA_GET, //! event for VA get image 116 EVENT_VA_CONFIG, //! event for VA query config 117 EVENT_VA_SURFACE, //! event for VA create surface 118 EVENT_VA_FREE_SURFACE, //! event for VA destroy surface 119 EVENT_VA_DERIVE, //! event for VA derive surface to image 120 EVENT_VA_MAP, //! event for VA map buffer 121 EVENT_VA_UNMAP, //! event for VA unmap buffer 122 EVENT_VA_LOCK, //! event for VA lock surface 123 EVENT_VA_UNLOCK, //! event for VA unlock surface 124 EVENT_VA_BUFFER, //! event for VA create buffer 125 EVENT_VA_FREE_BUFFER, //! event for VA destroy buffer 126 EVENT_VA_IMAGE, //! event for VA create image 127 EVENT_VA_FREE_IMAGE, //! event for VA destroy image 128 EVENT_VA_PUT, //! event for VA put image 129 EVENT_PIPE_EXE, //! event for pipeline execute 130 EVENT_PIPE_PACKET, //! event for pipeline ActivatePacket 131 EVENT_DDI_CREATE_DEVICE, //! event for Refactor DDI Create Device 132 EVENT_DDI_DESTROY_DEVICE, //! event for Refactor DDI Destroy Device 133 EVENT_DDI_DESTROY_RESOURCE_INFO, //! event for Refactor DDI Destroy Resource Info 134 EVENT_DDI_SYNC_CALLBACK, //! event for Refactor DDI Sync Callback 135 EVENT_DDI_LOCK_SYNC_CALLBACK, //! event for Refactor DDI Lock Sync 136 EVENT_DDI_TRIM_RESIDENCY_MEDIA, //! event for Refactor DDI Trim Residency Media 137 EVENT_DDI_TRIM_RESIDENCY_MEDIA_INTERNAL, //! event for Refactor DDI Trim Residency Media Internal 138 EVENT_DDI_UPDATE_MEDIA_RESIDENCY_LIST, //! event for Refactor DDI Update Media Residency List 139 EVENT_DDI_IS_PROTECTION_ENABLED, //! event for Refactor DDI Is Protection Enable 140 EVENT_DDI_PROTECTION_TRIGGERED, //! event for Refactor DDI Protection Triggered 141 EVENT_DDI_INIT_ARBITRATOR_SESSION_RES, //! event for Refactor DDI Init Arbitrator Session Res 142 EVENT_DDI_IS_OVERLAY_OR_FULLSCREEN_REQUIRED, //! event for Refactor DDI Is Overlay Or Fullscreen Required 143 EVENT_DDI_MEDIA_MEM_DECOMP_CALLBACK, //! event for Refactor DDI Media Mem Decomp Callback 144 EVENT_DDI_MEDIA_MEM_COPY_CALLBACK, //! event for Refactor DDI Media Mem Copy Callback 145 EVENT_DDI_GET_TRANSCRYPTED_SHADER, //! event for Refactor DDI Get Transcrypted Shader 146 EVENT_DDI_CLEAR_VIDEO_VIEW, //! event for Refactor DDI Clear Video View 147 EVENT_GPU_CONTEXT_CREATE, //! event for gpu context create 148 EVENT_GPU_CONTEXT_DESTROY, //! event for gpu context destroy 149 EVENT_PIC_PARAM_AVC, //! event for AVC picture param 150 EVENT_PIC_PARAM_HEVC, //! event for HEVC picture param 151 EVENT_PIC_PARAM_VP9, //! event for VP9 picture param 152 EVENT_PIC_PARAM_AV1, //! event for AV1 picture param 153 EVENT_MEDIA_LOG, //! event for media log 154 EVENT_MEDIA_LOG_RESERVE, //! event for more media log 155 EVENT_MEDIA_ERR, //! event for media error 156 EVENT_MEDIA_ERR_RESERVE, //! event for more media error 157 EVENT_DECODE_DDI_11_GETPROFILECOUNT, //! event for Decode Get Profile Count 158 EVENT_DECODE_DDI_11_GETPROFILE, //! event for Decode Get Profile 159 EVENT_DECODE_DDI_11_CHECKFORMAT, //! event for Decode Check Format 160 EVENT_DECODE_DDI_11_GETCONFIGCOUNT, //! event for Decode Config Count 161 EVENT_DECODE_DDI_11_GETCONFIG, //! event for Decode Config 162 EVENT_DECODE_DDI_11_GETBUFFERTYPECOUNT, //! event for Decode Buffer Count 163 EVENT_DECODE_DDI_11_GETBUFFERINFO, //! event for Decode Buffer Info 164 EVENT_DECODE_DDI_11_CREATEVIDEODECODER, //! event for Decode Create Device 165 EVENT_DECODE_DDI_11_CREATEOUTPUTVIEW, //! event for Decode Create Output View 166 EVENT_DECODE_DDI_11_BEGINFRAME, //! event for Decode Begin Frame 167 EVENT_DECODE_DDI_11_SUBMITBUFFERS, //! event for Decode Execute 168 EVENT_DECODE_DDI_11_EXTENSIONEXECUTE, //! event for Decode Extension Execute 169 EVENT_DECODE_DDI_11_ENDFRAME, //! event for Decode End Frame 170 EVENT_DECODE_DDI_11_DESTROYOUTPUTVIEW, //! event for Decode Destroy Output View 171 EVENT_DECODE_DDI_11_DESTROYVIDEODECODER, //! event for Decode Destroy Device 172 EVENT_DECODE_BUFFER_PICPARAM_VP9, //! event for Decode VP9 Pic Paramters 173 EVENT_DECODE_BUFFER_SEGPARAM_VP9, //! event for Decode VP9 Segment Paramters 174 EVENT_DECODE_BUFFER_SLICEPARAM_VP9, //! event for Decode VP9 Slice Paramters 175 EVENT_DECODE_BUFFER_Bitstream, //! event for Decode Bitstream 176 EVENT_DECODE_CMD_HCP_PIPEMODESELECT, //! event for Decode HcpPipeModeSelect Cmd 177 EVENT_DECODE_CMD_HCP_SURFACESTATE, //! event for Decode HcpSurfaceState Cmd 178 EVENT_DECODE_CMD_HCP_PIPEBUFADDRSTATE, //! event for Decode HcpPipeBufAddrState Cmd 179 EVENT_DECODE_CMD_HCP_INDOBJBASEADDRSTATE, //! event for Decode HcpIndObjBaseAddrState Cmd 180 EVENT_DECODE_CMD_HCP_SEGMENTSTATE_VP9, //! event for Decode HcpVp9SegmentState Cmd 181 EVENT_DECODE_CMD_HCP_PICSTATE_VP9, //! event for Decode HcpVp9PicState Cmd 182 EVENT_DECODE_CMD_HCP_BSDOBJECT, //! event for Decode HcpBsdObject Cmd 183 EVENT_DECODE_BUFFER_PICPARAM_AV1, //! event for Decode AV1 Pic Paramters 184 EVENT_DECODE_BUFFER_SEGPARAM_AV1, //! event for Decode AV1 Segment Paramters 185 EVENT_DECODE_BUFFER_FILMGRAINPARAM_AV1, //! event for Decode AV1 Film Grain Paramters 186 EVENT_DECODE_BUFFER_TILEPARAM_AV1, //! event for Decode AV1 Tile Paramters 187 EVENT_DECODE_BUFFER_PICPARAM_AVC, //! event for Decode AVC Pic Paramters 188 EVENT_DECODE_BUFFER_SLICEPARAM_AVC, //! event for Decode AVC Slice Paramters 189 EVENT_DECODE_BUFFER_PICPARAM_HEVC, //! event for Decode HEVC Pic Paramters 190 EVENT_DECODE_BUFFER_REXTPICPARAM_HEVC, //! event for Decode HEVC REXT Pic Paramters 191 EVENT_DECODE_BUFFER_SCCPICPARAM_HEVC, //! event for Decode HEVC SCC Pic Paramters 192 EVENT_DECODE_BUFFER_SLICEPARAM_HEVC, //! event for Decode HEVC Slice Paramters 193 EVENT_DECODE_CMD_HCP_PICSTATE_HEVC, //! event for Decode HcpHevcPicState Cmd 194 EVENT_DECODE_CMD_HCP_REXTPICSTATE_HEVC, //! event for Decode HcpHevcRextPicState Cmd 195 EVENT_DECODE_CMD_HCP_SCCPICSTATE_HEVC, //! event for Decode HcpHevcSccPicState Cmd 196 EVENT_DECODE_FEATURE_MMC, //! event for Decode Feature MMC 197 EVENT_DECODE_FEATURE_VT_SCALABILITY, //! event for Decode Feature Virtual Tile Scalability 198 EVENT_DECODE_FEATURE_RT_SCALABILITY, //! event for Decode Feature Real Tile Scalability 199 EVENT_DECODE_FEATURE_DECODEMODE_REPORT, //! event for Decode Feature Decode Mode Report 200 EVENT_DECODE_SURFACE_DUMPINFO, //! event for Decode Yuv Surface Info 201 } MEDIA_EVENT; 202 203 typedef enum _MEDIA_EVENT_TYPE 204 { 205 EVENT_TYPE_INFO = 0, //! function information event 206 EVENT_TYPE_START = 1, //! function entry event 207 EVENT_TYPE_END = 2, //! function exit event 208 EVENT_TYPE_INFO2 = 3, //! function extra information event 209 } MEDIA_EVENT_TYPE; 210 211 typedef enum _MT_LEVEL 212 { 213 MT_VERBOSE = 0, //! verbos runtime log 214 MT_NORMAL = 1, //! normal runtime log 215 MT_CRITICAL = 2, //! critical runtime log 216 } MT_LEVEL; 217 218 #pragma pack(1) 219 typedef struct _MT_PARAM 220 { 221 int32_t id; 222 int64_t value; 223 } MT_PARAM; 224 #pragma pack() 225 226 //! 227 //! \def media trace log id 228 //! |------------|------------------------------------| total 32bits 229 //! 8bits comp id 24bits user specific id 230 //! 231 typedef enum _MT_LOG_ID 232 { 233 MT_LOG_ID_BASE = 0x00000000, // marker for tool, don't change this line 234 MT_ERR_MEM_ALLOC, 235 MT_ERR_GRAPHIC_ALLOC, 236 MT_ERR_NULL_CHECK, 237 MT_ERR_HR_CHECK, 238 MT_ERR_MOS_STATUS_CHECK, 239 MT_ERR_CONDITION_CHECK, 240 MT_ERR_INVALID_ARG, 241 MT_ERR_LOCK_SURFACE, 242 MT_MOS_GPUCXT_CREATE, 243 MT_MOS_GPUCXT_DESTROY, 244 MT_MOS_GPUCXT_GET, 245 MT_MOS_GPUCXT_PRIMARIES, 246 MT_MOS_ADDCMD, 247 MT_MOS_GPUCXT_SETHANDLE, 248 MT_MOS_SYNC, 249 MT_LOG_ID_CP_BASE = 0x01000000, 250 MT_CP_HAL_NOT_INITIALIZED, 251 MT_CP_HAL_FAIL, 252 MT_CP_HAL_KEY_RULE, 253 MT_CP_HAL_FW_RULE, 254 MT_CP_HAL_EPID_CERT, 255 MT_CP_HAL_VERIFY_TRANS_KERNEL, 256 MT_CP_HAL_METADATA, 257 MT_CP_HAL_EPID_STATUS, 258 MT_CP_HAL_STATUS_CHECK, 259 MT_CP_PROVISION_CERT_CHECK, 260 MT_CP_PROVISION_CERT_NOT_FOUND, 261 MT_CP_KERNEL_RULE, 262 MT_CP_KERNEL_TRANSCRYPT, 263 MT_CP_BUFFER_RULE, 264 MT_CP_MEM_COPY, 265 MT_CP_TRANSCODE_SESSION, 266 MT_CP_KEY_EXCHANGE, 267 MT_CP_CMD_BUFFER_OVERFLOW, 268 MT_CP_CAST_FAIL, 269 MT_CP_PED_PACKET_SIZE_CHECK, 270 MT_CP_CRYPT_COPY_PARAM, 271 MT_CP_INVALID_ENCRYPT_TYPE, 272 MT_CP_INVALID_CACHED_KEY, 273 MT_CP_STATUS_UNINITIALIZED, 274 MT_CP_HAL_QUERY_STATUS, 275 MT_CP_HAl_ROOT_FAIL, 276 MT_CP_ENCRYPT_FAIL, 277 MT_CP_SESSION_INIT, 278 MT_CP_SESSION_CLEANUP, 279 MT_CP_SESSION_CREATE, 280 MT_CP_RETRY_FAIL, 281 MT_CP_CMD_SEND_FAIL, 282 MT_CP_CMD_EXECUTE_FAIL, 283 MT_CP_INVALID_SLOT, 284 MT_CP_INIT_FW, 285 MT_CP_COMMUNICATION_FAIL, 286 MT_CP_INVALID_BUFFER, 287 MT_CP_RESOURCE_DATA, 288 MT_CP_IO_MSG, 289 MT_CP_MHW_ID_BASE = 0x01004000, 290 MT_CP_MHW_INTERFACE_CREATE_FAIL, 291 MT_CP_MHW_ALLOCATION_FAIL, 292 MT_CP_MHW_UNIT_NOT_SUPPORT, 293 MT_CP_MHW_UNSUPPORTED, 294 MT_CP_MHW_IV_SIZE, 295 MT_CP_MHW_INVALID_KEY, 296 MT_CP_MHW_EARLY_EXIT_CHECK, 297 MT_CP_MHW_STATUS_READ, 298 MT_CP_DDI_ID_BASE = 0x01005000, 299 MT_CP_DDI_CAPS, 300 MT_LOG_ID_VP_BASE = 0x02000000, 301 MT_VP_CREATE, 302 MT_VP_DESTROY, 303 MT_VP_BLT, 304 MT_VP_BLT_START, 305 MT_VP_BLT_END, 306 MT_VP_BLT_BYPSSED, 307 MT_VP_BLT_FORCE_COLORFILL, 308 MT_VP_BLT_PROCAMP_PARAM, 309 MT_VP_BLT_DN_PARAM, 310 MT_VP_BLT_IEF_PARAM, 311 MT_VP_BLT_IECP_PARAM, 312 MT_VP_BLT_SR_PARAM, 313 MT_VP_BLT_RENDERPASS_DATA, 314 MT_VP_CLEARVIEW, 315 MT_VP_BLT_SETSTATE, 316 MT_VP_BLT_TARGETSURF, 317 MT_VP_BLT_INPUTSURF, 318 MT_VP_BLT_SRC_RECT, 319 MT_VP_BLT_DST_RECT, 320 MT_VP_BLT_TARGET_RECT, 321 MT_VP_BLT_HDRPARAM, 322 MT_VP_BLT_FDFBPARAM, 323 MT_VP_BLT_SEGMENTPARAM, 324 MT_VP_BLT_MCPYPARAM, 325 MT_VP_USERFEATURE_CTRL, 326 MT_VP_HAL_ID_BASE = 0x02000400, 327 MT_VP_HAL_PIPELINE_ADAPTER, 328 MT_VP_HAL_PIPELINE_ADAPTER_EXT_ENTRY, 329 MT_VP_HAL_PIPELINE_ADAPTER_EXT_EXIT, 330 MT_VP_HAL_PIPELINE, 331 MT_VP_HAL_PIPELINE_PREPARE, 332 MT_VP_HAL_PIPELINE_EXT, 333 MT_VP_HAL_POLICY, 334 MT_VP_HAL_HWFILTER, 335 MT_VP_HAL_SWWFILTER, 336 MT_VP_HAL_INIT, 337 MT_VP_HAL_DESTROY, 338 MT_VP_HAL_RENDER, 339 MT_VP_HAL_RENDER_VE, 340 MT_VP_HAL_RENDER_VE_ISNEEDED, 341 MT_VP_HAL_RENDER_VE_GETOUTPUTPIPE, 342 MT_VP_HAL_RENDER_SFC, 343 MT_VP_HAL_RENDER_COMPOSITE, 344 MT_VP_HAL_ALLOC_SURF, 345 MT_VP_HAL_REALLOC_SURF, 346 MT_VP_HAL_SWWFILTER_ADD, 347 MT_VP_HAL_ONNEWFRAME_PROC_START, 348 MT_VP_HAL_ONNEWFRAME_PROC_END, 349 MT_VP_HAL_POLICY_GET_EXTCAPS4FTR, 350 MT_VP_HAL_POLICY_GET_INPIPECAPS, 351 MT_VP_HAL_POLICY_GET_OUTPIPECAPS, 352 MT_VP_HAL_POLICY_INIT_EXECCAPS, 353 MT_VP_HAL_FC_SCALINGINFO, 354 MT_VP_MHW_ID_BASE = 0x02002000, 355 MT_VP_MHW_VE_SURFSTATE_INPUT, 356 MT_VP_MHW_VE_SURFSTATE_OUT, 357 MT_VP_MHW_VE_SURFSTATE_DNOUT, 358 MT_VP_MHW_VE_SURFSTATE_SKINSCORE, 359 MT_VP_MHW_VE_SURFSTATE_STMM, 360 MT_VP_MHW_VE_SCALABILITY, 361 MT_VP_MHW_VE_ADJUST_SURFPARAM, 362 MT_VP_KERNEL_ID_BASE = 0x02003000, 363 MT_VP_KERNEL_CSC, 364 MT_VP_KERNEL_RULE, 365 MT_VP_KERNEL_LIST_ADD, 366 MT_MEDIA_COPY_ID_BASE = 0x02004000, 367 MT_VE_DECOMP_COPY, 368 MT_MEDIA_COPY, 369 MT_MEDIA_COPY_BLT, 370 MT_MEDIA_COPY_RENDER, 371 MT_MEDIA_COPY_VE, 372 MT_LOG_ID_DEC_BASE = 0x03000000, 373 MT_DEC_HEVC, 374 MT_LOG_ID_ENC_BASE = 0x04000000, 375 } MT_LOG_ID; 376 377 //! 378 //! \def media trace parameter id 379 //! 380 typedef enum _MT_PARAM_ID 381 { 382 MT_PARAM_ID_BASE = 0, 383 MT_ERROR_CODE, 384 MT_COMPONENT, 385 MT_SUB_COMPONENT, 386 MT_CODE_LINE, 387 MT_GENERIC_VALUE, 388 MT_PRODUCT_FAMILY, 389 MT_SURF_PTR, 390 MT_SURF_ALLOC_HANDLE, 391 MT_SURF_WIDTH, 392 MT_SURF_HEIGHT, 393 MT_SURF_PITCH, 394 MT_SURF_MOS_FORMAT, 395 MT_SURF_TILE_TYPE, 396 MT_SURF_TILE_MODE, 397 MT_SURF_COMP_ABLE, 398 MT_SURF_COMP_MODE, 399 MT_SURF_GMM_FLAG_GPU, 400 MT_SURF_GMM_FLAG_INF, 401 MT_SURF_GMM_FLAG_WA, 402 MT_SURF_RES_ARRAYSIZE, 403 MT_SURF_RES_INDEX, 404 MT_SURF_CP_TAG, 405 MT_SURF_IS_INPUT, 406 MT_SURF_IS_OUTPUT, 407 MT_RECT_LEFT, 408 MT_RECT_TOP, 409 MT_RECT_RIGHT, 410 MT_RECT_BOTTOM, 411 MT_SYSMEM_PTR, 412 MT_SYSMEM_WIDTH, 413 MT_SYSMEM_HSTRIDE, 414 MT_SYSMEM_VSTRIDE, 415 MT_FUNC_START, 416 MT_FUNC_END, 417 MT_FUNC_RET, 418 MT_VIEW_TYPE, 419 MT_PARAM_ID_MOS_BASE = 0x00001000, 420 MT_MOS_STATUS, 421 MT_MOS_GPU_NODE, 422 MT_MOS_GPUCXT_MGR_PTR, 423 MT_MOS_GPUCXT_PTR, 424 MT_MOS_GPUCXT_HANDLE, 425 MT_MOS_GPUCXT_COUNT, 426 MT_MOS_GPUCXT_NUMPRIMARIES, 427 MT_MOS_GPUCXT, 428 MT_MOS_SYNC_HAZARDTYPE, 429 MT_MOS_SYNC_BUSYCTX, 430 MT_MOS_SYNC_REQCTX, 431 MT_PARAM_ID_CP_BASE = 0x01000000, 432 MT_CP_SESSION_TYPE, 433 MT_CP_SESSION_MODE, 434 MT_CP_STREAM_ID, 435 MT_CP_FW_CAPABILITY, 436 MT_CP_KEY_LENGTH, 437 MT_CP_COMMAND_ID, 438 MT_CP_COMMAND, 439 MT_CP_GROUP_ID, 440 MT_CP_METADATA_INFO_VERSION, 441 MT_CP_FW_API_VERSION, 442 MT_CP_BUFFER_NAME, 443 MT_CP_CMD_BUFFER_REMAIN, 444 MT_CP_PRODUCT_FAMILY_ID, 445 MT_CP_KEY_EXCHANGE_TYPE, 446 MT_CP_QUERY_OPERATION, 447 MT_CP_CRYPT_COPY_ADDR_CMD, 448 MT_CP_CRYPT_COPY_CMD, 449 MT_CP_IV_SIZE, 450 MT_CP_MHW_GPR0, 451 MT_CP_MHW_SCRATCH_BUFFER, 452 MT_CP_ENCRYPT_TYPE, 453 MT_CP_COMMAND_TYPE, 454 MT_CP_CPTO_TYPE, 455 MT_CP_CAPS, 456 MT_PARAM_ID_VP_BASE = 0x02000000, 457 MT_VP_SCALINGMODE_SR, 458 MT_PARAM_ID_VP_FTR_BASE = 0x02000200, 459 MT_VP_SKU_FTR_VERING, 460 MT_VP_SKU_FTR_MCPY, 461 MT_VP_UF_CTRL_DISABLE_VEOUT, 462 MT_VP_UF_CTRL_DISABLE_SFC, 463 MT_VP_UF_CTRL_CCS, 464 MT_PARAM_ID_VP_BLT_BASE = 0x02000300, 465 MT_VP_BLT_PARAM_DATA, 466 MT_VP_BLT_PARAM_FLAG, 467 MT_VP_BLT_SRC_COUNT, 468 MT_VP_BLT_AUTO_PROCESSING_MODE, 469 MT_VP_BLT_OUTPUT_FRAME, 470 MT_VP_BLT_STREAM_COUNT, 471 MT_VP_BLT_SAMPLE_TYPE, 472 MT_VP_BLT_CSPACE, 473 MT_VP_BLT_ROTATION, 474 MT_VP_BLT_SURF_TYPE, 475 MT_VP_BLT_CHROMASITING, 476 MT_VP_BLT_HDRPARAM_EOTF, 477 MT_VP_BLT_HDRPARAM_MAX_DISPLUMA, 478 MT_VP_BLT_HDRPARAM_MIN_DISPLUMA, 479 MT_VP_BLT_HDRPARAM_MAXCLL, 480 MT_VP_BLT_HDRPARAM_MAXFALL, 481 MT_VP_BLT_FDFBPARAM_MODE, 482 MT_VP_BLT_FDFBPARAM_FACECOUNT, 483 MT_VP_BLT_FDFBPARAM_FBMAXFACECOUNT, 484 MT_VP_BLT_SR_MODE, 485 MT_PARAM_ID_VP_HAL_BASE = 0x02000400, 486 MT_VP_HAL_APO, 487 MT_VP_HAL_PTR, 488 MT_VP_HAL_PIPE_CNT, 489 MT_VP_HAL_INTER_SURF_TYPE, 490 MT_VP_RENDERPASS_FLAG_COMP_NEEDED, 491 MT_VP_RENDERPASS_FLAG_HDR_NEEDED, 492 MT_VP_RENDERPASS_FLAG_FASTCOLORFILL, 493 MT_VP_RENDERPASS_FLAG_BYPASS_HDRKERNEL, 494 MT_VP_RENDERPASS_FLAG_USEVEHDRSFC, 495 MT_VP_RENDERDATA_OUTPUT_PIPE, 496 MT_VP_RENDERDATA_2PASS_CSC, 497 MT_VP_RENDERDATA_HDRCSCCUSDS, 498 MT_VP_RENDERDATA_HDRSFC, 499 MT_VP_RENDERDATA_HDR3DLUT, 500 MT_VP_RENDERDATA_HDR1DLUT, 501 MT_VP_RENDERDATA_BPROCAMP, 502 MT_VP_RENDERDATA_BIECP, 503 MT_VP_RENDERDATA_DV_TONAMAPPING, 504 MT_VP_RENDER_VE_2PASS_SFC, 505 MT_VP_RENDER_VE_USE_HDRTEMPSURF, 506 MT_VP_RENDER_VE_HDRMODE, 507 MT_VP_RENDER_VE_NEEDED, 508 MT_VP_RENDER_VE_HITLIMITATION, 509 MT_VP_RENDER_VE_8KFORCERENDER, 510 MT_VP_RENDER_VE_CROPPING, 511 MT_VP_RENDER_VE_SFCONLYFORVE, 512 MT_VP_RENDER_VE_COMPBYPASSFEASIBLE, 513 MT_VP_HAL_PIPE_INDEX, 514 MT_VP_HAL_PIPE_ISINPUT, 515 MT_VP_HAL_FEATUERTYPE, 516 MT_VP_HAL_ENGINECAPS, 517 MT_VP_HAL_ENGINECAPS_EN, 518 MT_VP_HAL_ENGINECAPS_VE_NEEDED, 519 MT_VP_HAL_ENGINECAPS_SFC_NEEDED, 520 MT_VP_HAL_ENGINECAPS_RENDER_NEEDED, 521 MT_VP_HAL_ENGINECAPS_FC_SUPPORT, 522 MT_VP_HAL_ENGINECAPS_ISOLATED, 523 MT_VP_HAL_EXECCAPS, 524 MT_VP_HAL_EXECCAPS_VE, 525 MT_VP_HAL_EXECCAPS_SFC, 526 MT_VP_HAL_EXECCAPS_RENDER, 527 MT_VP_HAL_EXECCAPS_COMP, 528 MT_VP_HAL_EXECCAPS_OUTPIPE_FTRINUSE, 529 MT_VP_HAL_EXECCAPS_IECP, 530 MT_VP_HAL_EXECCAPS_FORCE_CSC2RENDER, 531 MT_VP_HAL_EXECCAPS_DI_2NDFIELD, 532 MT_VP_HAL_ONNEWFRAME_COUNTER, 533 MT_VP_HAL_SCALING_MODE, 534 MT_VP_HAL_SCALING_MODE_FORCE, 535 MT_VP_HAL_SAMPLER_TYPE, 536 MT_VP_HAL_SAMPLER_FILTERMODE, 537 MT_VP_HAL_SAMPLER_INDEX, 538 MT_VP_HAL_FC_LAYER, 539 MT_VP_HAL_FC_LAYER_SURFENTRY, 540 MT_PARAM_ID_VP_MHW_BASE = 0x02002000, 541 MT_VP_MHW_VE_SCALABILITY_EN, 542 MT_VP_MHW_VE_SCALABILITY_USE_SFC, 543 MT_VP_MHW_VE_SCALABILITY_IDX, 544 MT_PARAM_ID_VP_KERNEL_BASE = 0x02003000, 545 MT_VP_KERNEL_CSPACE, 546 MT_VP_KERNEL_RULE_ID, 547 MT_VP_KERNEL_RULE_LAYERNUM, 548 MT_VP_KERNEL_RULE_SEARCH_STATE, 549 MT_VP_KERNEL_ID, 550 MT_PARAM_ID_MEDIA_COPY_BASE = 0x02004000, 551 MT_VE_DECOMP_COPY_SURF_LOCK_STATUS, 552 MT_MEDIA_COPY_CAPS, 553 MT_MEDIA_COPY_DIRECTION, 554 MT_MEDIA_COPY_METHOD, 555 MT_PARAM_ID_DEC_BASE = 0x03000000, 556 MT_DEC_HUC_ERROR_STATUS2, 557 MT_CODEC_HAL_MODE, 558 MT_PARAM_ID_ENC_BASE = 0x04000000, 559 } MT_PARAM_ID; 560 561 #endif 562