/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2_cls.c | 1072 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 1074 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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H A D | mvpp2.h | 135 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2_cls.c | 1072 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 1074 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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H A D | mvpp2.h | 135 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2_cls.c | 1072 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 1074 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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H A D | mvpp2.h | 135 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/Net/Pp2Dxe/ |
H A D | Mvpp2LibHw.h | 85 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/ |
H A D | mvpp2.c | 129 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2552 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2554 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/ |
H A D | mvpp2.c | 129 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2552 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2554 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/ |
H A D | mvpp2.c | 129 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2552 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2554 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 138 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 macro 2541 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set() 2543 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
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