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Searched refs:MVPP2_PRS_RI_CPU_CODE_RX_SPEC (Results 1 – 25 of 70) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.h196 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
H A Dmvpp2_prs.c1410 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1423 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1741 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip4_init()
1831 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip6_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.h196 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
H A Dmvpp2_prs.c1410 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1423 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1741 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip4_init()
1831 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip6_init()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.h196 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
H A Dmvpp2_prs.c1410 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1423 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1741 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip4_init()
1831 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_ip6_init()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/Net/Pp2Dxe/
H A DMvpp2Lib.c1644 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL, in Mvpp2PrsEtypeInit()
1658 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL, in Mvpp2PrsEtypeInit()
1993 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL, in Mvpp2PrsIp4Init()
2088 MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL, in Mvpp2PrsIp6Init()
H A DMvpp2LibHw.h1742 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/
H A Dmvpp2.c788 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2064 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2077 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/
H A Dmvpp2.c788 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2064 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2077 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/
H A Dmvpp2.c788 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2064 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2077 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/
H A Dmvpp2.c780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) macro
2053 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2066 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()

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