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Searched refs:MVPP2_PRS_SRAM_DATA_REG (Results 1 – 25 of 70) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.c35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
2149 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
H A Dmvpp2.h82 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.c35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
2149 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
H A Dmvpp2.h82 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_prs.c35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
2149 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
H A Dmvpp2.h82 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/
H A Dmvpp2.c107 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1424 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1451 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2225 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/
H A Dmvpp2.c107 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1424 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1451 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2225 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/
H A Dmvpp2.c107 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1424 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1451 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2225 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/net/
H A Dmvpp2.c116 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1413 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1440 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2214 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/net/
H A Dmvpp2.c107 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) macro
1424 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1451 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
2225 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()

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