| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 385 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 385 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 385 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/Net/Pp2Dxe/ |
| H A D | Mvpp2LibHw.h | 228 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 312 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3813 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3834 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 312 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3813 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3834 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 312 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3813 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3834 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 312 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3813 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3834 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff macro
3872 MVPP2_TXP_SCHED_ENQ_MASK; in mvpp2_egress_disable()
3893 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
|