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Searched refs:M_RL (Results 1 – 23 of 23) sorted by relevance

/dports/emulators/almostti/AlmostTI-DougMelton-Source/Z80/
H A DCodesCB.h26 case RL_B: M_RL(R->BC.B.h);break; case RL_C: M_RL(R->BC.B.l);break;
27 case RL_D: M_RL(R->DE.B.h);break; case RL_E: M_RL(R->DE.B.l);break;
28 case RL_H: M_RL(R->HL.B.h);break; case RL_L: M_RL(R->HL.B.l);break;
29 case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
30 case RL_A: M_RL(R->AF.B.h);break;
H A DCodesXCB.h16 case RL_xHL: I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
H A DZ80.c85 #define M_RL(Rg) \ macro
/dports/emulators/darcnes/darcnes/
H A Dmz80opc2.h28 case RL_B: M_RL(R->BC.B.h);break; case RL_C: M_RL(R->BC.B.l);break;
29 case RL_D: M_RL(R->DE.B.h);break; case RL_E: M_RL(R->DE.B.l);break;
30 case RL_H: M_RL(R->HL.B.h);break; case RL_L: M_RL(R->HL.B.l);break;
31 case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
32 case RL_A: M_RL(R->AF.B.h);break;
H A Dmz80opc3.h18 case RL_xHL: I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
H A Dmz80.c552 #define M_RL(Rg) \ macro
/dports/emulators/quasi88/quasi88-0.6.4/src/
H A Dz80-codeCB.h30 case RL_B: M_RL(z80->BC.B.h); break;
31 case RL_C: M_RL(z80->BC.B.l); break;
32 case RL_D: M_RL(z80->DE.B.h); break;
33 case RL_E: M_RL(z80->DE.B.l); break;
34 case RL_H: M_RL(z80->HL.B.h); break;
35 case RL_L: M_RL(z80->HL.B.l); break;
37 I=M_RDMEM(z80->HL.W); M_RL(I); M_WRMEM(z80->HL.W,I); break;
38 case RL_A: M_RL(z80->AF.B.h); break;
H A Dz80-codeXXCB.h28 case RL_B: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->BC.B.h=I; break;
29 case RL_C: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->BC.B.l=I; break;
30 case RL_D: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->DE.B.h=I; break;
31 case RL_E: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->DE.B.l=I; break;
32 case RL_H: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->HL.B.h=I; break;
33 case RL_L: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->HL.B.l=I; break;
34 case RL_xHL: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); break;
35 case RL_A: I=M_RDMEM(J.W); M_RL(I); M_WRMEM(J.W,I); z80->AF.B.h=I; break;
H A Dz80.c170 #define M_RL(reg) do{ \ macro
/dports/games/libretro-fmsx/fmsx-libretro-c2c26b1/Z80/
H A DCodesCB.h26 case RL_B: M_RL(R->BC.B.h);break; case RL_C: M_RL(R->BC.B.l);break;
27 case RL_D: M_RL(R->DE.B.h);break; case RL_E: M_RL(R->DE.B.l);break;
28 case RL_H: M_RL(R->HL.B.h);break; case RL_L: M_RL(R->HL.B.l);break;
29 case RL_xHL: I=RdZ80(R->HL.W);M_RL(I);WrZ80(R->HL.W,I);break;
30 case RL_A: M_RL(R->AF.B.h);break;
H A DCodesXCB.h16 case RL_xHL: I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
H A DZ80.c87 #define M_RL(Rg) \ macro
/dports/emulators/mess/mame-mame0226/src/devices/cpu/tlcs900/
H A Ddasm900.h39 M_RES, M_RET, M_RETD, M_RETI, M_RL, M_RLC, enumerator
H A Ddasm900.cpp77 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
161 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
665 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
786 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
790 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
954 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
958 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
1122 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
1126 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
/dports/emulators/mame/mame-mame0226/src/devices/cpu/tlcs900/
H A Ddasm900.h39 M_RES, M_RET, M_RETD, M_RETI, M_RL, M_RLC, enumerator
H A Ddasm900.cpp77 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
161 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
665 { M_RLC, O_M, O_NONE }, { M_RRC, O_M, O_NONE }, { M_RL, O_M, O_NONE }, { M_RR, O_M, O_NONE },
786 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
790 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
954 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
958 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
1122 { M_RLC, O_I8, O_R }, { M_RRC, O_I8, O_R }, { M_RL, O_I8, O_R }, { M_RR, O_I8, O_R },
1126 { M_RLC, O_A, O_R }, { M_RRC, O_A, O_R }, { M_RL, O_A, O_R }, { M_RR, O_A, O_R },
/dports/emulators/adamem/adamem-1.0_4/
H A DZ80CDx86.h478 #define M_RL(Reg) \ macro
H A DZ80.c1180 M_RL(i); in rl_xhl()
1189 M_RL(i); in rl_xix()
1198 M_RL(i); in rl_xiy()
1201 static void rl_a(void) { M_RL(R.AF.B.h); } in rl_a()
1202 static void rl_b(void) { M_RL(R.BC.B.h); } in rl_b()
1203 static void rl_c(void) { M_RL(R.BC.B.l); } in rl_c()
1204 static void rl_d(void) { M_RL(R.DE.B.h); } in rl_d()
1205 static void rl_e(void) { M_RL(R.DE.B.l); } in rl_e()
1206 static void rl_h(void) { M_RL(R.HL.B.h); } in rl_h()
1207 static void rl_l(void) { M_RL(R.HL.B.l); } in rl_l()
H A DZ80Codes.h83 #define M_RL(Reg) \ macro
/dports/devel/cxmon/cxmon-3.2/src/
H A Dmon_z80.cpp67 M_RETN, M_RL, M_RLA, M_RLC, M_RLCA, M_RLD, M_RR, M_RRA, M_RRC, M_RRCA, enumerator
380 case 2: mnem = M_RL; break; in disass_cb()
/dports/devel/tpasm/tpasm1.11/processors/
H A D8051.c380 M_RL[]= variable
474 {"rl", MODES(M_RL) },
H A Dz80.c783 M_RL[]= variable
991 {"rl", MODES(M_RL) },
/dports/emulators/xcpc/xcpc-20070122/src/dev/
H A Dz80cpu_tables.h261 M_RL(dest); \
266 I=(*z80cpu->mreq_rd)(z80cpu,addr); M_RL(I); (*z80cpu->mreq_wr)(z80cpu,addr,I); \
750 #define M_RL(Rg) \ macro