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Searched refs:NO_REQNO (Results 1 – 16 of 16) sorted by relevance

/dports/devel/avr-gdb/gdb-7.3.1/sim/frv/
H A Dmloop.in268 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
279 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
282 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
355 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
366 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
369 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
371 if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
374 frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
H A Dcache.h244 #define NO_REQNO 0xffffffff macro
H A Dprofile.c117 {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address. */
618 if (frv_insn_fetch_buffer[j].reqno != NO_REQNO in run_caches()
622 frv_insn_fetch_buffer[j].reqno = NO_REQNO; in run_caches()
H A Dcache.c988 req->reqno = NO_REQNO; in frv_cache_request_store()
1036 req->reqno = NO_REQNO; in frv_cache_request_preload()
1059 req->reqno = NO_REQNO; in frv_cache_request_unlock()
/dports/devel/gdb761/gdb-7.6.1/sim/frv/
H A Dmloop.in267 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
278 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
281 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
354 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
365 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
368 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
370 if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
373 frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
H A Dcache.h243 #define NO_REQNO 0xffffffff macro
H A Dprofile.c116 {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address. */
617 if (frv_insn_fetch_buffer[j].reqno != NO_REQNO in run_caches()
621 frv_insn_fetch_buffer[j].reqno = NO_REQNO; in run_caches()
H A Dcache.c987 req->reqno = NO_REQNO; in frv_cache_request_store()
1035 req->reqno = NO_REQNO; in frv_cache_request_preload()
1058 req->reqno = NO_REQNO; in frv_cache_request_unlock()
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/frv/
H A Dmloop.in268 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
279 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
282 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
355 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
366 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
369 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
371 if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
374 frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
H A Dcache.h244 #define NO_REQNO 0xffffffff macro
H A Dprofile.c117 {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address. */
618 if (frv_insn_fetch_buffer[j].reqno != NO_REQNO in run_caches()
622 frv_insn_fetch_buffer[j].reqno = NO_REQNO; in run_caches()
H A Dcache.c988 req->reqno = NO_REQNO; in frv_cache_request_store()
1036 req->reqno = NO_REQNO; in frv_cache_request_preload()
1059 req->reqno = NO_REQNO; in frv_cache_request_unlock()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/frv/
H A Dmloop.in268 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
279 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
282 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
355 while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
366 if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
369 frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
371 if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
374 frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
H A Dcache.h244 #define NO_REQNO 0xffffffff macro
H A Dprofile.c117 {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address. */
618 if (frv_insn_fetch_buffer[j].reqno != NO_REQNO in run_caches()
622 frv_insn_fetch_buffer[j].reqno = NO_REQNO; in run_caches()
H A Dcache.c988 req->reqno = NO_REQNO; in frv_cache_request_store()
1036 req->reqno = NO_REQNO; in frv_cache_request_preload()
1059 req->reqno = NO_REQNO; in frv_cache_request_unlock()