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Searched refs:NumVecs (Results 1 – 25 of 125) sorted by relevance

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/dports/devel/llvm70/llvm-7.0.1.src/lib/Analysis/
H A DVectorUtils.cpp495 unsigned NumVecs) { in createInterleaveMask() argument
498 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
553 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
554 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
560 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
562 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
569 if (NumVecs % 2 != 0) in concatenateVectors()
570 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
573 NumVecs = ResList.size(); in concatenateVectors()
574 } while (NumVecs > 1); in concatenateVectors()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1805 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
1841 if (NumVecs == 1) in SelectVLD()
1844 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
1920 if (NumVecs == 1) { in SelectVLD()
1944 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2115 if (NumVecs != 3) { in SelectVLDSTLane()
2147 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2173 if (NumVecs == 2) { in SelectVLDSTLane()
2223 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2236 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1746 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
1782 if (NumVecs == 1) in SelectVLD()
1785 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
1861 if (NumVecs == 1) { in SelectVLD()
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2056 if (NumVecs != 3) { in SelectVLDSTLane()
2086 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2112 if (NumVecs == 2) { in SelectVLDSTLane()
2162 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2175 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1747 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
1781 if (NumVecs == 1) in SelectVLD()
1784 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
1861 if (NumVecs == 1) { in SelectVLD()
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2058 if (NumVecs != 3) { in SelectVLDSTLane()
2088 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2114 if (NumVecs == 2) { in SelectVLDSTLane()
2164 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2177 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2012 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2048 if (NumVecs == 1) in SelectVLD()
2051 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2127 if (NumVecs == 1) { in SelectVLD()
2151 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2322 if (NumVecs != 3) { in SelectVLDSTLane()
2354 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2380 if (NumVecs == 2) { in SelectVLDSTLane()
2692 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2705 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2012 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2048 if (NumVecs == 1) in SelectVLD()
2051 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2127 if (NumVecs == 1) { in SelectVLD()
2151 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2322 if (NumVecs != 3) { in SelectVLDSTLane()
2354 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2380 if (NumVecs == 2) { in SelectVLDSTLane()
2692 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2705 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2012 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2048 if (NumVecs == 1) in SelectVLD()
2051 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2127 if (NumVecs == 1) { in SelectVLD()
2151 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2322 if (NumVecs != 3) { in SelectVLDSTLane()
2354 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2380 if (NumVecs == 2) { in SelectVLDSTLane()
2692 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2705 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2060 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2098 if (NumVecs == 1) in SelectVLD()
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2177 if (NumVecs == 1) { in SelectVLD()
2202 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2376 if (NumVecs != 3) { in SelectVLDSTLane()
2410 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2436 if (NumVecs == 2) { in SelectVLDSTLane()
2896 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2909 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2060 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2098 if (NumVecs == 1) in SelectVLD()
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2177 if (NumVecs == 1) { in SelectVLD()
2202 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2376 if (NumVecs != 3) { in SelectVLDSTLane()
2410 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2436 if (NumVecs == 2) { in SelectVLDSTLane()
2896 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2909 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2060 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2098 if (NumVecs == 1) in SelectVLD()
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2177 if (NumVecs == 1) { in SelectVLD()
2202 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2376 if (NumVecs != 3) { in SelectVLDSTLane()
2410 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2436 if (NumVecs == 2) { in SelectVLDSTLane()
2896 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2909 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2060 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2098 if (NumVecs == 1) in SelectVLD()
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2177 if (NumVecs == 1) { in SelectVLD()
2202 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2376 if (NumVecs != 3) { in SelectVLDSTLane()
2410 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2436 if (NumVecs == 2) { in SelectVLDSTLane()
2896 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2909 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2060 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2098 if (NumVecs == 1) in SelectVLD()
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2177 if (NumVecs == 1) { in SelectVLD()
2202 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2376 if (NumVecs != 3) { in SelectVLDSTLane()
2410 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2436 if (NumVecs == 2) { in SelectVLDSTLane()
2896 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2909 if (NumVecs != 3) { in SelectVLDDup()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1124 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1)); in SelectTable()
1235 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1239 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1264 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1268 if (NumVecs == 1) in SelectPostLoad()
1271 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1384 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1391 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1425 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoadLane()
1429 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1093 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1)); in SelectTable()
1204 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1208 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1233 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1237 if (NumVecs == 1) in SelectPostLoad()
1240 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1353 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1360 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1394 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoadLane()
1398 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1093 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1204 for (unsigned i = 0; i < NumVecs; ++i)
1208 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1234 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1238 if (NumVecs == 1)
1241 for (unsigned i = 0; i < NumVecs; ++i)
1355 for (unsigned i = 0; i < NumVecs; ++i) {
1362 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1396 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1400 if (NumVecs == 1) {
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1374 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1378 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1403 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1407 if (NumVecs == 1) in SelectPostLoad()
1410 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1466 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1471 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1622 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1629 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1667 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1369 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1373 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1398 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1402 if (NumVecs == 1) in SelectPostLoad()
1405 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1452 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1457 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1609 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1616 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1654 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1416 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1420 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1448 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1452 if (NumVecs == 1) in SelectPostLoad()
1455 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1511 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1516 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1667 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1674 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1712 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1374 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1378 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1406 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1410 if (NumVecs == 1) in SelectPostLoad()
1413 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1469 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1474 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1625 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1632 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1670 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1368 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1372 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1397 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1401 if (NumVecs == 1) in SelectPostLoad()
1404 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1460 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1465 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1616 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1623 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1661 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1416 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1420 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1448 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1452 if (NumVecs == 1) in SelectPostLoad()
1455 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1511 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1516 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1667 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1674 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1712 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1416 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1420 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1448 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1452 if (NumVecs == 1) in SelectPostLoad()
1455 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1511 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1516 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1667 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1674 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1712 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1416 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1420 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1448 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1452 if (NumVecs == 1) in SelectPostLoad()
1455 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1511 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1516 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1667 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1674 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1712 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1416 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1420 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1448 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1452 if (NumVecs == 1) in SelectPostLoad()
1455 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1511 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1516 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1667 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1674 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1712 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1374 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1378 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1406 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1410 if (NumVecs == 1) in SelectPostLoad()
1413 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1469 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1474 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1625 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1632 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1670 if (NumVecs == 1) { in SelectPostLoadLane()
[all …]

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