| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_bist.c | 47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
132 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
508 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
518 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
540 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
551 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
|