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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A D	bitreverse.mir	46 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 49 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 51 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 126 ; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] 129 ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] 131 ; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) 197 ; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]] 198 ; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]] 200 ; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
/dports/cad/alliance/alliance/src/genlib/doc/
H A D	man_dpgen_or4.sgm	`3 <refentry id="DPGEN-OR4"> 14 <refpurpose> OR4 Macro-Generator </refpurpose>`
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-reduce-or.mir	115 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]] 117 ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]] 161 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT8]], [[ANYEXT9]] 173 ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]] 305 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]] 307 ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]] 344 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]] 346 ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[OR4]] 389 ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]] 489 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]] [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	121 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 122 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 124 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 200 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 201 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 203 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 325 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 326 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 328 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 404 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/capacity.tst/lca100kgate/
H A D	OR4.v	`1 module OR4(a, b, c, d, z); module`
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fptrunc.mir	123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 124 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 126 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 204 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 206 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] 331 ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32) 333 ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]] 410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]] [all …]

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