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Searched refs:OR_SCY_7_CLK (Results 1 – 25 of 87) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/configs/
H A DRBC823.h355 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
H A DR360MPI.h381 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/include/
H A Dmpc8xx.h243 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ macro

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