| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_hdmi.h | 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
|