/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 Register OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 Register OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 205 unsigned OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 230 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 297 unsigned OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 322 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 332 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned OrigSrc1 = MI.getOperand(2).getReg(); 222 if (!MRI->def_empty(OrigSrc1)) { 224 MRI->def_instr_begin(OrigSrc1); 231 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) 298 unsigned OrigSrc1 = MI.getOperand(2).getReg(); 321 if (!MRI->def_empty(OrigSrc1)) { 323 MRI->def_instr_begin(OrigSrc1); 333 if (MRI->hasOneNonDBGUse(OrigSrc1)) { 351 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned OrigSrc1 = MI.getOperand(2).getReg(); in isProfitableToTransform() local 222 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform() 224 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform() 231 if (MOSrc1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform() 298 unsigned OrigSrc1 = MI.getOperand(2).getReg(); in transformInstruction() local 321 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction() 323 MRI->def_instr_begin(OrigSrc1); in transformInstruction() 333 if (MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction() 351 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
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