| /dports/sysutils/u-boot-chip/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/board/phytec/phycore_imx8mp/ |
| H A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|