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Searched refs:PCIL0_CFGBASE (Results 1 – 13 of 13) sorted by relevance

/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/
H A Dppc440.h109 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
121 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
122 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
123 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
132 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
137 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
140 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
142 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
145 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
148 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
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H A Dppc440gp.h56 #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
57 #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
H A Dppc440sp.h82 #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
83 #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
H A Dppc440gx.h86 #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
87 #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
H A Dppc440spe.h98 #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
99 #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
H A Dppc460ex_gt.h208 #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
209 #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/
H A Dppc440.h1771 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
1783 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
1784 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
1785 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
1821 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
1826 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
1829 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
1831 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
1834 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
1837 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
[all …]