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Searched refs:PCI_BAR2 (Results 1 – 9 of 9) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dpucdata.c2154 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2164 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2174 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2184 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2195 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2206 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2236 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2248 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2260 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
2273 { PUC_PORT_TYPE_COM, PCI_BAR2, 0x00,
[all …]
H A Digma.c368 if (pci_mapreg_map(pa, PCI_BAR2, PCI_MAPREG_TYPE_MEM, in igma_attach()
H A Dpcireg.h440 #define PCI_BAR2 0x18 macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/cardbus/
H A Dif_ex_cardbus.c76 #define CARDBUS_3C575BTX_FUNCSTAT_PCIREG PCI_BAR2 /* means 0x18 */
H A Dcardbus.c515 cardbus_conf_write(cc, cf, tag, PCI_BAR2, 0); in cardbus_rescan()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
H A DVlvCommonDefinitions.h44 #define PCI_BAR2 0x0018 ///< Base Address Register 2 macro
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
H A DVlvCommonDefinitions.h38 #define PCI_BAR2 0x0018 ///< Base Address Register 2
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Include/
H A DQNCCommonDefinitions.h31 #define PCI_BAR2 0x0018 // Base Address Register 2 macro
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkSouthCluster/Include/
H A DIohCommonDefinitions.h31 #define PCI_BAR2 0x0018 // Base Address Register 2 macro