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Searched refs:PHY_ENDIANNESS (Results 1 – 6 of 6) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/
H A Daurora_axis_mac.v6 parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} constant
143 generate if (PHY_ENDIANNESS == "BIG") begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/
H A Daurora_axis_mac.v6 parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} constant
143 generate if (PHY_ENDIANNESS == "BIG") begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/
H A Daurora_axis_mac.v6 parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} constant
143 generate if (PHY_ENDIANNESS == "BIG") begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_sfpp_io_core.v355 .PHY_ENDIANNESS ("LITTLE"),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dn3xx_mgt_io_core.v525 .PHY_ENDIANNESS ("LITTLE"),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_mgt_io_core.v674 .PHY_ENDIANNESS ("LITTLE"),