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/dports/math/ploticus-nox11/pl240src/src/
H A Dexecline.c113 if( PLL.nlines > 0 && PLL.nlines < PLL.maxproclines-1 ) {
115 strcpy( PLL.procline[ PLL.nlines ], "\n" );
130 PLL.objlen[ PLL.nobj ] = PLL.nlines - nlhold;
190 strcpy( PLL.objname[ PLL.nobj ], "" );
191 PLL.objstart[ PLL.nobj ] = PLL.nlines;
248 PLL.procline[ PLL.nlines ][ buflen ] = '\0';
250 if( PLL.nlines >= PLL.maxproclines-1 ) {
395 PLL.curline = PLL.objstart[j];
396 procstop = PLL.objstart[j] + PLL.objlen[j];
400 PLL.curline = PLL.objstart[ PLL.nobj ];
[all …]
H A Dproc_getdata.c97 datastart = PLL.curline-1; in PLP_getdata()
98 strcpy( PLL.procline[ PLL.curline-1 ], lineval ); /* remove 'data:' */ in PLP_getdata()
100 else datastart = PLL.curline; in PLP_getdata()
102 ndatarows = (PLL.curline - datastart); /* was -1 */ in PLP_getdata()
108 scriptstart = PLL.curline-1; in PLP_getdata()
109 strcpy( PLL.procline[ PLL.curline-1 ], lineval ); /* remove 'filter:' */ in PLP_getdata()
111 else scriptstart = PLL.curline; in PLP_getdata()
117 for( j = 0; PLL.procline[i][j] != '\0'; j++ ) { in PLP_getdata()
118 if( PLL.procline[i][j] == '#' && PLL.procline[i][j+1] == '#' ) { in PLP_getdata()
119 PLL.procline[i][j] = ' '; in PLP_getdata()
[all …]
/dports/math/ploticus/pl240src/src/
H A Dexecline.c113 if( PLL.nlines > 0 && PLL.nlines < PLL.maxproclines-1 ) {
115 strcpy( PLL.procline[ PLL.nlines ], "\n" );
130 PLL.objlen[ PLL.nobj ] = PLL.nlines - nlhold;
190 strcpy( PLL.objname[ PLL.nobj ], "" );
191 PLL.objstart[ PLL.nobj ] = PLL.nlines;
248 PLL.procline[ PLL.nlines ][ buflen ] = '\0';
250 if( PLL.nlines >= PLL.maxproclines-1 ) {
395 PLL.curline = PLL.objstart[j];
396 procstop = PLL.objstart[j] + PLL.objlen[j];
400 PLL.curline = PLL.objstart[ PLL.nobj ];
[all …]
H A Dproc_getdata.c97 datastart = PLL.curline-1; in PLP_getdata()
98 strcpy( PLL.procline[ PLL.curline-1 ], lineval ); /* remove 'data:' */ in PLP_getdata()
100 else datastart = PLL.curline; in PLP_getdata()
102 ndatarows = (PLL.curline - datastart); /* was -1 */ in PLP_getdata()
108 scriptstart = PLL.curline-1; in PLP_getdata()
109 strcpy( PLL.procline[ PLL.curline-1 ], lineval ); /* remove 'filter:' */ in PLP_getdata()
111 else scriptstart = PLL.curline; in PLP_getdata()
117 for( j = 0; PLL.procline[i][j] != '\0'; j++ ) { in PLP_getdata()
118 if( PLL.procline[i][j] == '#' && PLL.procline[i][j+1] == '#' ) { in PLP_getdata()
119 PLL.procline[i][j] = ' '; in PLP_getdata()
[all …]
/dports/lang/micropython/micropython-1.17/ports/stm32/
H A Dsystem_stm32.c220 RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM; in SystemClock_Config()
221 RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN; in SystemClock_Config()
222 RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP; in SystemClock_Config()
223 RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ; in SystemClock_Config()
224 RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR; in SystemClock_Config()
241 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; in SystemClock_Config()
292 RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM; in SystemClock_Config()
293 RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN; in SystemClock_Config()
294 RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP; in SystemClock_Config()
303 RCC_OscInitStruct.PLL.PLLFRACN = 0; in SystemClock_Config()
[all …]
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/
H A Dstm32g4xx_hal_rcc.c618 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); in HAL_RCC_OscConfig()
620 if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) in HAL_RCC_OscConfig()
625 if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) in HAL_RCC_OscConfig()
652 RCC_OscInitStruct->PLL.PLLM, in HAL_RCC_OscConfig()
653 RCC_OscInitStruct->PLL.PLLN, in HAL_RCC_OscConfig()
654 RCC_OscInitStruct->PLL.PLLP, in HAL_RCC_OscConfig()
655 RCC_OscInitStruct->PLL.PLLQ, in HAL_RCC_OscConfig()
656 RCC_OscInitStruct->PLL.PLLR); in HAL_RCC_OscConfig()
701 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) in HAL_RCC_OscConfig()
1216 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; in HAL_RCC_GetOscConfig()
[all …]
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_rcc.c707 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); in HAL_RCC_OscConfig()
708 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) in HAL_RCC_OscConfig()
713 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) in HAL_RCC_OscConfig()
740 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, in HAL_RCC_OscConfig()
741 RCC_OscInitStruct->PLL.PLLM, in HAL_RCC_OscConfig()
742 RCC_OscInitStruct->PLL.PLLN, in HAL_RCC_OscConfig()
743 RCC_OscInitStruct->PLL.PLLP, in HAL_RCC_OscConfig()
744 RCC_OscInitStruct->PLL.PLLQ, in HAL_RCC_OscConfig()
745 RCC_OscInitStruct->PLL.PLLR); in HAL_RCC_OscConfig()
1433 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; in HAL_RCC_GetOscConfig()
[all …]
/dports/devel/trellis/prjtrellis-5eb0ad87/fuzzers/ECP5/090-pll_routing/
H A Dpllroute.ncl12 comp PLL
15 cellmodel-name PLL;
25 (PLL, LOCK),
27 (PLL, RST);
H A Dpllroute_85k.ncl12 comp PLL
15 cellmodel-name PLL;
25 (PLL, LOCK),
27 (PLL, RST);
H A Dpllroute_25k.ncl12 comp PLL
15 cellmodel-name PLL;
25 (PLL, LOCK),
27 (PLL, RST);
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock

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