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Searched refs:PLL3RGE (Results 1 – 3 of 3) sorted by relevance

/dports/lang/micropython/micropython-1.17/ports/stm32/
H A Dsystem_stm32.c337 PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; in SystemClock_Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_rcc_ex.c1387 …PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3R… in HAL_RCCEx_GetPeriphCLKConfig()
2803 assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); in RCCEx_PLL3_Config()
2838 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; in RCCEx_PLL3_Config()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_hal_rcc_ex.h96 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range member