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Searched refs:PLL4_CLOCK (Results 1 – 25 of 63) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c23 PLL4_CLOCK, enumerator
33 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
241 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
685 case PLL4_CLOCK: in config_pll_clk()
856 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
957 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c23 PLL4_CLOCK, enumerator
33 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
241 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
685 case PLL4_CLOCK: in config_pll_clk()
856 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
957 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c23 PLL4_CLOCK, enumerator
33 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
241 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
685 case PLL4_CLOCK: in config_pll_clk()
856 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
957 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c23 PLL4_CLOCK, enumerator
33 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
241 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
685 case PLL4_CLOCK: in config_pll_clk()
856 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
957 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c25 PLL4_CLOCK, enumerator
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
687 case PLL4_CLOCK: in config_pll_clk()
858 return config_pll_clk(PLL4_CLOCK, &pll_param); in config_ldb_clk()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()

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