| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 840 #define PLLE_SS_CNTL 0x68 macro
896 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
899 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
919 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
931 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
933 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
936 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
940 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
942 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 557 #define PLLE_SS_CNTL 0x68 macro
647 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
650 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
671 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
684 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 932 #define PLLE_SS_CNTL 0x68 macro
988 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
991 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1011 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1023 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1025 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1032 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1034 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 932 #define PLLE_SS_CNTL 0x68 macro
988 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
991 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1011 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1023 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1025 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1032 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1034 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 935 #define PLLE_SS_CNTL 0x68 macro
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 932 #define PLLE_SS_CNTL 0x68 macro
988 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
991 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1011 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1023 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1025 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1032 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1034 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 932 #define PLLE_SS_CNTL 0x68 macro
988 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
991 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1011 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1023 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1025 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1028 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1032 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
1034 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); in tegra_plle_enable()
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