| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 561 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
648 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
679 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
745 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
|