| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/at91/ |
| H A D | clk-pll.c | 18 #define PLL_DIV_MAX PLL_DIV_MASK macro
153 if (tmpdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
165 if (maxdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
166 maxdiv = PLL_DIV_MAX; in clk_pll_get_best_div_mul()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/at91/ |
| H A D | clk-pll.c | 18 #define PLL_DIV_MAX PLL_DIV_MASK macro
153 if (tmpdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
165 if (maxdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
166 maxdiv = PLL_DIV_MAX; in clk_pll_get_best_div_mul()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/at91/ |
| H A D | clk-pll.c | 18 #define PLL_DIV_MAX PLL_DIV_MASK macro
153 if (tmpdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
165 if (maxdiv > PLL_DIV_MAX) in clk_pll_get_best_div_mul()
166 maxdiv = PLL_DIV_MAX; in clk_pll_get_best_div_mul()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 189 #define PLL_DIV_MAX 3200 macro
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 189 #define PLL_DIV_MAX 3200 macro
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 189 #define PLL_DIV_MAX 3200 macro
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 194 #define PLL_DIV_MAX 3200 macro
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 189 #define PLL_DIV_MAX 3200 macro
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
|