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Searched refs:PLL_MODE_NORM (Results 1 – 25 of 127) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/rockchip/
H A Dclk-pll.c22 #define PLL_MODE_NORM 0x1 macro
208 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
441 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
690 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/rockchip/
H A Dclk-pll.c22 #define PLL_MODE_NORM 0x1 macro
208 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
441 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
690 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/rockchip/
H A Dclk-pll.c22 #define PLL_MODE_NORM 0x1 macro
208 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
441 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
690 if (cur_parent == PLL_MODE_NORM) { in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c77 PLL_MODE_NORM, enumerator
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c77 PLL_MODE_NORM, enumerator
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c77 PLL_MODE_NORM, enumerator
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3328.c82 PLL_MODE_NORM, enumerator
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c77 PLL_MODE_NORM, enumerator
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()

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