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Searched refs:PLL_SLOW_MODE (Results 1 – 25 of 40) sorted by relevance

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/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h19 #define PLL_SLOW_MODE 0 macro
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h19 #define PLL_SLOW_MODE 0 macro
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h19 #define PLL_SLOW_MODE 0 macro
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h19 #define PLL_SLOW_MODE 0 macro
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h19 #define PLL_SLOW_MODE 0 macro
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro

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