/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/mach-imx/mx7ulp/ |
H A D | soc.c | 18 #define PMC0_BASE_ADDR 0x410a1000 macro 129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); in ldo_mode_is_enabled() 146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); in init_ldo_mode() 172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); in init_ldo_mode() 175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); in init_ldo_mode()
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