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Searched refs:PREAMBLE5 (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/
H A Dmdio_master.v37 PREAMBLE5 = 5, constant
258 state <= PREAMBLE5;
260 PREAMBLE5: begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/simple_gemac/
H A Dmdio.v50 PREAMBLE5 = 5, constant
316 state <= PREAMBLE5;
318 PREAMBLE5: begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Dwishbone_if.v100 PREAMBLE5 = 5, constant
494 state <= PREAMBLE5;
496 PREAMBLE5: begin