1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #ifndef __PROGRAMMER_H__
21 #define __PROGRAMMER_H__ 1
22
23 #include <stdint.h>
24
25 #include "flash.h" /* for chipaddr and flashctx */
26
27 enum programmer {
28 #if CONFIG_INTERNAL == 1
29 PROGRAMMER_INTERNAL,
30 #endif
31 #if CONFIG_DUMMY == 1
32 PROGRAMMER_DUMMY,
33 #endif
34 #if CONFIG_NIC3COM == 1
35 PROGRAMMER_NIC3COM,
36 #endif
37 #if CONFIG_NICREALTEK == 1
38 PROGRAMMER_NICREALTEK,
39 #endif
40 #if CONFIG_NICNATSEMI == 1
41 PROGRAMMER_NICNATSEMI,
42 #endif
43 #if CONFIG_GFXNVIDIA == 1
44 PROGRAMMER_GFXNVIDIA,
45 #endif
46 #if CONFIG_DRKAISER == 1
47 PROGRAMMER_DRKAISER,
48 #endif
49 #if CONFIG_SATASII == 1
50 PROGRAMMER_SATASII,
51 #endif
52 #if CONFIG_ATAHPT == 1
53 PROGRAMMER_ATAHPT,
54 #endif
55 #if CONFIG_ATAVIA == 1
56 PROGRAMMER_ATAVIA,
57 #endif
58 #if CONFIG_ATAPROMISE == 1
59 PROGRAMMER_ATAPROMISE,
60 #endif
61 #if CONFIG_IT8212 == 1
62 PROGRAMMER_IT8212,
63 #endif
64 #if CONFIG_FT2232_SPI == 1
65 PROGRAMMER_FT2232_SPI,
66 #endif
67 #if CONFIG_SERPROG == 1
68 PROGRAMMER_SERPROG,
69 #endif
70 #if CONFIG_BUSPIRATE_SPI == 1
71 PROGRAMMER_BUSPIRATE_SPI,
72 #endif
73 #if CONFIG_DEDIPROG == 1
74 PROGRAMMER_DEDIPROG,
75 #endif
76 #if CONFIG_DEVELOPERBOX_SPI == 1
77 PROGRAMMER_DEVELOPERBOX_SPI,
78 #endif
79 #if CONFIG_RAYER_SPI == 1
80 PROGRAMMER_RAYER_SPI,
81 #endif
82 #if CONFIG_PONY_SPI == 1
83 PROGRAMMER_PONY_SPI,
84 #endif
85 #if CONFIG_NICINTEL == 1
86 PROGRAMMER_NICINTEL,
87 #endif
88 #if CONFIG_NICINTEL_SPI == 1
89 PROGRAMMER_NICINTEL_SPI,
90 #endif
91 #if CONFIG_NICINTEL_EEPROM == 1
92 PROGRAMMER_NICINTEL_EEPROM,
93 #endif
94 #if CONFIG_OGP_SPI == 1
95 PROGRAMMER_OGP_SPI,
96 #endif
97 #if CONFIG_SATAMV == 1
98 PROGRAMMER_SATAMV,
99 #endif
100 #if CONFIG_LINUX_MTD == 1
101 PROGRAMMER_LINUX_MTD,
102 #endif
103 #if CONFIG_LINUX_SPI == 1
104 PROGRAMMER_LINUX_SPI,
105 #endif
106 #if CONFIG_USBBLASTER_SPI == 1
107 PROGRAMMER_USBBLASTER_SPI,
108 #endif
109 #if CONFIG_MSTARDDC_SPI == 1
110 PROGRAMMER_MSTARDDC_SPI,
111 #endif
112 #if CONFIG_PICKIT2_SPI == 1
113 PROGRAMMER_PICKIT2_SPI,
114 #endif
115 #if CONFIG_CH341A_SPI == 1
116 PROGRAMMER_CH341A_SPI,
117 #endif
118 #if CONFIG_DIGILENT_SPI == 1
119 PROGRAMMER_DIGILENT_SPI,
120 #endif
121 #if CONFIG_JLINK_SPI == 1
122 PROGRAMMER_JLINK_SPI,
123 #endif
124 #if CONFIG_NI845X_SPI == 1
125 PROGRAMMER_NI845X_SPI,
126 #endif
127 #if CONFIG_STLINKV3_SPI == 1
128 PROGRAMMER_STLINKV3_SPI,
129 #endif
130 PROGRAMMER_INVALID /* This must always be the last entry. */
131 };
132
133 enum programmer_type {
134 PCI = 1, /* to detect uninitialized values */
135 USB,
136 OTHER,
137 };
138
139 struct dev_entry {
140 uint16_t vendor_id;
141 uint16_t device_id;
142 const enum test_state status;
143 const char *vendor_name;
144 const char *device_name;
145 };
146
147 struct programmer_entry {
148 const char *name;
149 const enum programmer_type type;
150 union {
151 const struct dev_entry *const dev;
152 const char *const note;
153 } devs;
154
155 int (*init) (void);
156
157 void *(*map_flash_region) (const char *descr, uintptr_t phys_addr, size_t len);
158 void (*unmap_flash_region) (void *virt_addr, size_t len);
159
160 void (*delay) (unsigned int usecs);
161 };
162
163 extern const struct programmer_entry programmer_table[];
164
165 int programmer_init(enum programmer prog, const char *param);
166 int programmer_shutdown(void);
167
168 struct bitbang_spi_master {
169 /* Note that CS# is active low, so val=0 means the chip is active. */
170 void (*set_cs) (int val);
171 void (*set_sck) (int val);
172 void (*set_mosi) (int val);
173 int (*get_miso) (void);
174 void (*request_bus) (void);
175 void (*release_bus) (void);
176 /* optional functions to optimize xfers */
177 void (*set_sck_set_mosi) (int sck, int mosi);
178 int (*set_sck_get_miso) (int sck);
179 /* Length of half a clock period in usecs. */
180 unsigned int half_period;
181 };
182
183 #if NEED_PCI == 1
184 struct pci_dev;
185
186 /* pcidev.c */
187 // FIXME: This needs to be local, not global(?)
188 extern struct pci_access *pacc;
189 int pci_init_common(void);
190 uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
191 struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar);
192 /* rpci_write_* are reversible writes. The original PCI config space register
193 * contents will be restored on shutdown.
194 * To clone the pci_dev instances internally, the `pacc` global
195 * variable has to reference a pci_access method that is compatible
196 * with the given pci_dev handle. The referenced pci_access (not
197 * the variable) has to stay valid until the shutdown handlers are
198 * finished.
199 */
200 int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
201 int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
202 int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
203 #endif
204
205 #if CONFIG_INTERNAL == 1
206 struct penable {
207 uint16_t vendor_id;
208 uint16_t device_id;
209 enum chipbustype buses;
210 const enum test_state status;
211 const char *vendor_name;
212 const char *device_name;
213 int (*doit) (struct pci_dev *dev, const char *name);
214 };
215
216 extern const struct penable chipset_enables[];
217
218 enum board_match_phase {
219 P1,
220 P2,
221 P3
222 };
223
224 struct board_match {
225 /* Any device, but make it sensible, like the ISA bridge. */
226 uint16_t first_vendor;
227 uint16_t first_device;
228 uint16_t first_card_vendor;
229 uint16_t first_card_device;
230
231 /* Any device, but make it sensible, like
232 * the host bridge. May be NULL.
233 */
234 uint16_t second_vendor;
235 uint16_t second_device;
236 uint16_t second_card_vendor;
237 uint16_t second_card_device;
238
239 /* Pattern to match DMI entries. May be NULL. */
240 const char *dmi_pattern;
241
242 /* The vendor / part name from the coreboot table. May be NULL. */
243 const char *lb_vendor;
244 const char *lb_part;
245
246 enum board_match_phase phase;
247
248 const char *vendor_name;
249 const char *board_name;
250
251 int max_rom_decode_parallel;
252 const enum test_state status;
253 int (*enable) (void); /* May be NULL. */
254 };
255
256 extern const struct board_match board_matches[];
257
258 struct board_info {
259 const char *vendor;
260 const char *name;
261 const enum test_state working;
262 #ifdef CONFIG_PRINT_WIKI
263 const char *url;
264 const char *note;
265 #endif
266 };
267
268 extern const struct board_info boards_known[];
269 extern const struct board_info laptops_known[];
270 #endif
271
272 /* udelay.c */
273 void myusec_delay(unsigned int usecs);
274 void myusec_calibrate_delay(void);
275 void internal_sleep(unsigned int usecs);
276 void internal_delay(unsigned int usecs);
277
278 #if CONFIG_INTERNAL == 1
279 /* board_enable.c */
280 int selfcheck_board_enables(void);
281 int board_parse_parameter(const char *boardstring, char **vendor, char **model);
282 void w836xx_ext_enter(uint16_t port);
283 void w836xx_ext_leave(uint16_t port);
284 void probe_superio_winbond(void);
285 int it8705f_write_enable(uint8_t port);
286 uint8_t sio_read(uint16_t port, uint8_t reg);
287 void sio_write(uint16_t port, uint8_t reg, uint8_t data);
288 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
289 void board_handle_before_superio(void);
290 void board_handle_before_laptop(void);
291 int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model);
292
293 /* chipset_enable.c */
294 int chipset_flash_enable(void);
295
296 /* processor_enable.c */
297 int processor_flash_enable(void);
298 #endif
299
300 /* physmap.c */
301 void *physmap(const char *descr, uintptr_t phys_addr, size_t len);
302 void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len);
303 void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len);
304 void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len);
305 void physunmap(void *virt_addr, size_t len);
306 void physunmap_unaligned(void *virt_addr, size_t len);
307 #if CONFIG_INTERNAL == 1
308 int setup_cpu_msr(int cpu);
309 void cleanup_cpu_msr(void);
310
311 /* cbtable.c */
312 int cb_parse_table(const char **vendor, const char **model);
313 int cb_check_image(const uint8_t *bios, unsigned int size);
314
315 /* dmi.c */
316 #if defined(__i386__) || defined(__x86_64__)
317 extern int has_dmi_support;
318 void dmi_init(void);
319 int dmi_match(const char *pattern);
320 #endif // defined(__i386__) || defined(__x86_64__)
321
322 /* internal.c */
323 struct superio {
324 uint16_t vendor;
325 uint16_t port;
326 uint16_t model;
327 };
328 extern struct superio superios[];
329 extern int superio_count;
330 #define SUPERIO_VENDOR_NONE 0x0
331 #define SUPERIO_VENDOR_ITE 0x1
332 #define SUPERIO_VENDOR_WINBOND 0x2
333 #endif
334 #if NEED_PCI == 1
335 struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
336 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
337 struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
338 uint16_t card_vendor, uint16_t card_device);
339 #endif
340 int rget_io_perms(void);
341 #if CONFIG_INTERNAL == 1
342 extern int is_laptop;
343 extern int laptop_ok;
344 extern int force_boardenable;
345 extern int force_boardmismatch;
346 void probe_superio(void);
347 int register_superio(struct superio s);
348 extern enum chipbustype internal_buses_supported;
349 int internal_init(void);
350 #endif
351
352 /* hwaccess.c */
353 void mmio_writeb(uint8_t val, void *addr);
354 void mmio_writew(uint16_t val, void *addr);
355 void mmio_writel(uint32_t val, void *addr);
356 uint8_t mmio_readb(const void *addr);
357 uint16_t mmio_readw(const void *addr);
358 uint32_t mmio_readl(const void *addr);
359 void mmio_readn(const void *addr, uint8_t *buf, size_t len);
360 void mmio_le_writeb(uint8_t val, void *addr);
361 void mmio_le_writew(uint16_t val, void *addr);
362 void mmio_le_writel(uint32_t val, void *addr);
363 uint8_t mmio_le_readb(const void *addr);
364 uint16_t mmio_le_readw(const void *addr);
365 uint32_t mmio_le_readl(const void *addr);
366 #define pci_mmio_writeb mmio_le_writeb
367 #define pci_mmio_writew mmio_le_writew
368 #define pci_mmio_writel mmio_le_writel
369 #define pci_mmio_readb mmio_le_readb
370 #define pci_mmio_readw mmio_le_readw
371 #define pci_mmio_readl mmio_le_readl
372 void rmmio_writeb(uint8_t val, void *addr);
373 void rmmio_writew(uint16_t val, void *addr);
374 void rmmio_writel(uint32_t val, void *addr);
375 void rmmio_le_writeb(uint8_t val, void *addr);
376 void rmmio_le_writew(uint16_t val, void *addr);
377 void rmmio_le_writel(uint32_t val, void *addr);
378 #define pci_rmmio_writeb rmmio_le_writeb
379 #define pci_rmmio_writew rmmio_le_writew
380 #define pci_rmmio_writel rmmio_le_writel
381 void rmmio_valb(void *addr);
382 void rmmio_valw(void *addr);
383 void rmmio_vall(void *addr);
384
385 /* dummyflasher.c */
386 #if CONFIG_DUMMY == 1
387 int dummy_init(void);
388 void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len);
389 void dummy_unmap(void *virt_addr, size_t len);
390 #endif
391
392 /* nic3com.c */
393 #if CONFIG_NIC3COM == 1
394 int nic3com_init(void);
395 extern const struct dev_entry nics_3com[];
396 #endif
397
398 /* gfxnvidia.c */
399 #if CONFIG_GFXNVIDIA == 1
400 int gfxnvidia_init(void);
401 extern const struct dev_entry gfx_nvidia[];
402 #endif
403
404 /* drkaiser.c */
405 #if CONFIG_DRKAISER == 1
406 int drkaiser_init(void);
407 extern const struct dev_entry drkaiser_pcidev[];
408 #endif
409
410 /* nicrealtek.c */
411 #if CONFIG_NICREALTEK == 1
412 int nicrealtek_init(void);
413 extern const struct dev_entry nics_realtek[];
414 #endif
415
416 /* nicnatsemi.c */
417 #if CONFIG_NICNATSEMI == 1
418 int nicnatsemi_init(void);
419 extern const struct dev_entry nics_natsemi[];
420 #endif
421
422 /* nicintel.c */
423 #if CONFIG_NICINTEL == 1
424 int nicintel_init(void);
425 extern const struct dev_entry nics_intel[];
426 #endif
427
428 /* nicintel_spi.c */
429 #if CONFIG_NICINTEL_SPI == 1
430 int nicintel_spi_init(void);
431 extern const struct dev_entry nics_intel_spi[];
432 #endif
433
434 /* nicintel_eeprom.c */
435 #if CONFIG_NICINTEL_EEPROM == 1
436 int nicintel_ee_init(void);
437 extern const struct dev_entry nics_intel_ee[];
438 #endif
439
440 /* ogp_spi.c */
441 #if CONFIG_OGP_SPI == 1
442 int ogp_spi_init(void);
443 extern const struct dev_entry ogp_spi[];
444 #endif
445
446 /* satamv.c */
447 #if CONFIG_SATAMV == 1
448 int satamv_init(void);
449 extern const struct dev_entry satas_mv[];
450 #endif
451
452 /* satasii.c */
453 #if CONFIG_SATASII == 1
454 int satasii_init(void);
455 extern const struct dev_entry satas_sii[];
456 #endif
457
458 /* atahpt.c */
459 #if CONFIG_ATAHPT == 1
460 int atahpt_init(void);
461 extern const struct dev_entry ata_hpt[];
462 #endif
463
464 /* atavia.c */
465 #if CONFIG_ATAVIA == 1
466 int atavia_init(void);
467 void *atavia_map(const char *descr, uintptr_t phys_addr, size_t len);
468 extern const struct dev_entry ata_via[];
469 #endif
470
471 /* atapromise.c */
472 #if CONFIG_ATAPROMISE == 1
473 int atapromise_init(void);
474 void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len);
475 extern const struct dev_entry ata_promise[];
476 #endif
477
478 /* it8212.c */
479 #if CONFIG_IT8212 == 1
480 int it8212_init(void);
481 extern const struct dev_entry devs_it8212[];
482 #endif
483
484 /* ft2232_spi.c */
485 #if CONFIG_FT2232_SPI == 1
486 int ft2232_spi_init(void);
487 extern const struct dev_entry devs_ft2232spi[];
488 #endif
489
490 /* usbblaster_spi.c */
491 #if CONFIG_USBBLASTER_SPI == 1
492 int usbblaster_spi_init(void);
493 extern const struct dev_entry devs_usbblasterspi[];
494 #endif
495
496 /* mstarddc_spi.c */
497 #if CONFIG_MSTARDDC_SPI == 1
498 int mstarddc_spi_init(void);
499 #endif
500
501 /* pickit2_spi.c */
502 #if CONFIG_PICKIT2_SPI == 1
503 int pickit2_spi_init(void);
504 extern const struct dev_entry devs_pickit2_spi[];
505 #endif
506
507 /* stlinkv3_spi.c */
508 #if CONFIG_STLINKV3_SPI == 1
509 int stlinkv3_spi_init(void);
510 extern const struct dev_entry devs_stlinkv3_spi[];
511 #endif
512
513 /* rayer_spi.c */
514 #if CONFIG_RAYER_SPI == 1
515 int rayer_spi_init(void);
516 #endif
517
518 /* pony_spi.c */
519 #if CONFIG_PONY_SPI == 1
520 int pony_spi_init(void);
521 #endif
522
523 /* bitbang_spi.c */
524 int register_spi_bitbang_master(const struct bitbang_spi_master *master);
525
526 /* buspirate_spi.c */
527 #if CONFIG_BUSPIRATE_SPI == 1
528 int buspirate_spi_init(void);
529 #endif
530
531 /* linux_mtd.c */
532 #if CONFIG_LINUX_MTD == 1
533 int linux_mtd_init(void);
534 #endif
535
536 /* linux_spi.c */
537 #if CONFIG_LINUX_SPI == 1
538 int linux_spi_init(void);
539 #endif
540
541 /* dediprog.c */
542 #if CONFIG_DEDIPROG == 1
543 int dediprog_init(void);
544 extern const struct dev_entry devs_dediprog[];
545 #endif
546
547 /* developerbox_spi.c */
548 #if CONFIG_DEVELOPERBOX_SPI == 1
549 int developerbox_spi_init(void);
550 extern const struct dev_entry devs_developerbox_spi[];
551 #endif
552
553 /* ch341a_spi.c */
554 #if CONFIG_CH341A_SPI == 1
555 int ch341a_spi_init(void);
556 void ch341a_spi_delay(unsigned int usecs);
557 extern const struct dev_entry devs_ch341a_spi[];
558 #endif
559
560 /* digilent_spi.c */
561 #if CONFIG_DIGILENT_SPI == 1
562 int digilent_spi_init(void);
563 extern const struct dev_entry devs_digilent_spi[];
564 #endif
565
566 /* jlink_spi.c */
567 #if CONFIG_JLINK_SPI == 1
568 int jlink_spi_init(void);
569 #endif
570
571 /* ni845x_spi.c */
572 #if CONFIG_NI845X_SPI == 1
573 int ni845x_spi_init(void);
574 #endif
575
576 /* flashrom.c */
577 struct decode_sizes {
578 uint32_t parallel;
579 uint32_t lpc;
580 uint32_t fwh;
581 uint32_t spi;
582 };
583 // FIXME: These need to be local, not global
584 extern struct decode_sizes max_rom_decode;
585 extern int programmer_may_write;
586 extern unsigned long flashbase;
587 unsigned int count_max_decode_exceedings(const struct flashctx *flash);
588 char *extract_programmer_param(const char *param_name);
589
590 /* spi.c */
591 #define MAX_DATA_UNSPECIFIED 0
592 #define MAX_DATA_READ_UNLIMITED 64 * 1024
593 #define MAX_DATA_WRITE_UNLIMITED 256
594
595 #define SPI_MASTER_4BA (1U << 0) /**< Can handle 4-byte addresses */
596 #define SPI_MASTER_NO_4BA_MODES (1U << 1) /**< Compatibility modes (i.e. extended address
597 register, 4BA mode switch) don't work */
598
599 struct spi_master {
600 uint32_t features;
601 unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address).
602 unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address).
603 int (*command)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
604 const unsigned char *writearr, unsigned char *readarr);
605 int (*multicommand)(struct flashctx *flash, struct spi_command *cmds);
606
607 /* Optimized functions for this master */
608 int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
609 int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
610 int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
611 const void *data;
612 };
613
614 int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
615 const unsigned char *writearr, unsigned char *readarr);
616 int default_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds);
617 int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
618 int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
619 int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
620 int register_spi_master(const struct spi_master *mst);
621
622 /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
623 enum ich_chipset {
624 CHIPSET_ICH_UNKNOWN,
625 CHIPSET_ICH,
626 CHIPSET_ICH2345,
627 CHIPSET_ICH6,
628 CHIPSET_POULSBO, /* SCH U* */
629 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
630 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
631 CHIPSET_ICH7,
632 CHIPSET_ICH8,
633 CHIPSET_ICH9,
634 CHIPSET_ICH10,
635 CHIPSET_5_SERIES_IBEX_PEAK,
636 CHIPSET_6_SERIES_COUGAR_POINT,
637 CHIPSET_7_SERIES_PANTHER_POINT,
638 CHIPSET_8_SERIES_LYNX_POINT,
639 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */
640 CHIPSET_8_SERIES_LYNX_POINT_LP,
641 CHIPSET_8_SERIES_WELLSBURG,
642 CHIPSET_9_SERIES_WILDCAT_POINT,
643 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
644 CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
645 CHIPSET_C620_SERIES_LEWISBURG,
646 CHIPSET_300_SERIES_CANNON_POINT,
647 CHIPSET_APOLLO_LAKE,
648 };
649
650 /* ichspi.c */
651 #if CONFIG_INTERNAL == 1
652 int ich_init_spi(void *spibar, enum ich_chipset ich_generation);
653 int via_init_spi(uint32_t mmio_base);
654
655 /* amd_imc.c */
656 int amd_imc_shutdown(struct pci_dev *dev);
657
658 /* it85spi.c */
659 int it85xx_spi_init(struct superio s);
660
661 /* it87spi.c */
662 void enter_conf_mode_ite(uint16_t port);
663 void exit_conf_mode_ite(uint16_t port);
664 void probe_superio_ite(void);
665 int init_superio_ite(void);
666
667 #if CONFIG_LINUX_MTD == 1
668 /* trivial wrapper to avoid cluttering internal_init() with #if */
try_mtd(void)669 static inline int try_mtd(void) { return linux_mtd_init(); };
670 #else
try_mtd(void)671 static inline int try_mtd(void) { return 1; };
672 #endif
673
674 /* mcp6x_spi.c */
675 int mcp6x_spi_init(int want_spi);
676
677 /* sb600spi.c */
678 int sb600_probe_spi(struct pci_dev *dev);
679
680 /* wbsio_spi.c */
681 int wbsio_check_for_spi(void);
682 #endif
683
684 /* opaque.c */
685 struct opaque_master {
686 int max_data_read;
687 int max_data_write;
688 /* Specific functions for this master */
689 int (*probe) (struct flashctx *flash);
690 int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
691 int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
692 int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);
693 const void *data;
694 };
695 int register_opaque_master(const struct opaque_master *mst);
696
697 /* programmer.c */
698 int noop_shutdown(void);
699 void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len);
700 void fallback_unmap(void *virt_addr, size_t len);
701 void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
702 void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
703 void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
704 void fallback_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
705 uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr);
706 uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr);
707 void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
708 struct par_master {
709 void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr);
710 void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr);
711 void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr);
712 void (*chip_writen) (const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
713 uint8_t (*chip_readb) (const struct flashctx *flash, const chipaddr addr);
714 uint16_t (*chip_readw) (const struct flashctx *flash, const chipaddr addr);
715 uint32_t (*chip_readl) (const struct flashctx *flash, const chipaddr addr);
716 void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
717 const void *data;
718 };
719 int register_par_master(const struct par_master *mst, const enum chipbustype buses);
720 struct registered_master {
721 enum chipbustype buses_supported;
722 union {
723 struct par_master par;
724 struct spi_master spi;
725 struct opaque_master opaque;
726 };
727 };
728 extern struct registered_master registered_masters[];
729 extern int registered_master_count;
730 int register_master(const struct registered_master *mst);
731
732 /* serprog.c */
733 #if CONFIG_SERPROG == 1
734 int serprog_init(void);
735 void serprog_delay(unsigned int usecs);
736 void *serprog_map(const char *descr, uintptr_t phys_addr, size_t len);
737 #endif
738
739 /* serial.c */
740 #if IS_WINDOWS
741 typedef HANDLE fdtype;
742 #define SER_INV_FD INVALID_HANDLE_VALUE
743 #else
744 typedef int fdtype;
745 #define SER_INV_FD -1
746 #endif
747
748 void sp_flush_incoming(void);
749 fdtype sp_openserport(char *dev, int baud);
750 extern fdtype sp_fd;
751 int serialport_config(fdtype fd, int baud);
752 int serialport_shutdown(void *data);
753 int serialport_write(const unsigned char *buf, unsigned int writecnt);
754 int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, unsigned int timeout, unsigned int *really_wrote);
755 int serialport_read(unsigned char *buf, unsigned int readcnt);
756 int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned int timeout, unsigned int *really_read);
757
758 /* Serial port/pin mapping:
759
760 1 CD <-
761 2 RXD <-
762 3 TXD ->
763 4 DTR ->
764 5 GND --
765 6 DSR <-
766 7 RTS ->
767 8 CTS <-
768 9 RI <-
769 */
770 enum SP_PIN {
771 PIN_CD = 1,
772 PIN_RXD,
773 PIN_TXD,
774 PIN_DTR,
775 PIN_GND,
776 PIN_DSR,
777 PIN_RTS,
778 PIN_CTS,
779 PIN_RI,
780 };
781
782 void sp_set_pin(enum SP_PIN pin, int val);
783 int sp_get_pin(enum SP_PIN pin);
784
785 /* spi_master feature checks */
spi_master_4ba(const struct flashctx * const flash)786 static inline bool spi_master_4ba(const struct flashctx *const flash)
787 {
788 return flash->mst->buses_supported & BUS_SPI &&
789 flash->mst->spi.features & SPI_MASTER_4BA;
790 }
spi_master_no_4ba_modes(const struct flashctx * const flash)791 static inline bool spi_master_no_4ba_modes(const struct flashctx *const flash)
792 {
793 return flash->mst->buses_supported & BUS_SPI &&
794 flash->mst->spi.features & SPI_MASTER_NO_4BA_MODES;
795 }
796
797 /* usbdev.c */
798 struct libusb_device_handle;
799 struct libusb_context;
800 struct libusb_device_handle *usb_dev_get_by_vid_pid_serial(
801 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, const char *serialno);
802 struct libusb_device_handle *usb_dev_get_by_vid_pid_number(
803 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num);
804
805 #endif /* !__PROGRAMMER_H__ */
806