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Searched refs:PSIHB_REG (Results 1 – 25 of 30) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
657 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
662 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
682 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
707 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
801 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
815 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
817 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/ppc/
H A Dpnv_psi.c123 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) in pnv_pnor_read()
409 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
415 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
652 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
657 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
677 uint32_t reg = PSIHB_REG(addr);
702 uint32_t reg = PSIHB_REG(addr);
796 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
810 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
812 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
653 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
658 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
678 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
703 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
797 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
811 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
813 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
653 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
658 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
678 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
703 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
797 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
811 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
813 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
657 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
662 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
682 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
707 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
801 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
815 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
817 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/ppc/
H A Dpnv_psi.c117 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
403 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
409 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
634 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
639 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
662 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
686 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
780 uint32_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
794 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
796 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/ppc/
H A Dpnv_psi.c123 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
409 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
415 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
652 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
657 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
677 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
702 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
796 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
810 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
812 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
658 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
663 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
683 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
708 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
802 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
816 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
818 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/ppc/
H A Dpnv_psi.c124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) macro
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); in pnv_psi_mmio_read()
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); in pnv_psi_mmio_write()
658 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
663 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
683 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_read()
708 uint32_t reg = PSIHB_REG(addr); in pnv_psi_p9_mmio_write()
802 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_irq_set()
816 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_irq_set()
818 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_irq_set()
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/skiboot/hw/
H A Dphys-map.c74 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
200 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
278 { PSIHB_REG, 0, 0x0006030203000000ull, 0x0000000000100000ull },
H A Dpsi.c977 phys_map_get(chip->id, PSIHB_REG, 0, &addr, NULL); in psi_probe_p9()
994 phys_map_get(chip->id, PSIHB_REG, 0, &addr, NULL); in psi_probe_p10()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/include/
H A Dphys-map.h47 PSIHB_REG, enumerator
/dports/emulators/qemu42/qemu-4.2.1/roms/skiboot/include/
H A Dphys-map.h49 PSIHB_REG, enumerator
/dports/emulators/qemu5/qemu-5.2.0/roms/skiboot/include/
H A Dphys-map.h49 PSIHB_REG, enumerator
/dports/emulators/qemu-utils/qemu-4.2.1/roms/skiboot/include/
H A Dphys-map.h49 PSIHB_REG, enumerator
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/skiboot/include/
H A Dphys-map.h49 PSIHB_REG, enumerator
/dports/emulators/qemu60/qemu-6.0.0/roms/skiboot/include/
H A Dphys-map.h49 PSIHB_REG, enumerator
/dports/emulators/qemu/qemu-6.2.0/roms/skiboot/include/
H A Dphys-map.h40 PSIHB_REG, enumerator
/dports/emulators/qemu42/qemu-4.2.1/roms/skiboot/hw/
H A Dphys-map.c128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
H A Dpsi.c852 phys_map_get(chip->id, PSIHB_REG, 0, &addr, NULL); in psi_probe_p9()
/dports/emulators/qemu5/qemu-5.2.0/roms/skiboot/hw/
H A Dphys-map.c128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/hw/
H A Dphys-map.c112 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
/dports/emulators/qemu-utils/qemu-4.2.1/roms/skiboot/hw/
H A Dphys-map.c128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/skiboot/hw/
H A Dphys-map.c128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
/dports/emulators/qemu60/qemu-6.0.0/roms/skiboot/hw/
H A Dphys-map.c128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },

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