| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 856 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
878 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
921 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
940 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
970 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
997 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 633 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
643 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
778 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
805 if (!producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) { in ValidateLiveOuts()
837 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
860 if (QPRs->contains(RegMask.PhysReg)) { in ValidateLiveOuts()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 865 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
887 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
930 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
949 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
979 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1006 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 633 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
643 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
778 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
805 if (!producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) { in ValidateLiveOuts()
837 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
860 if (QPRs->contains(RegMask.PhysReg)) { in ValidateLiveOuts()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 865 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
887 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
930 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
949 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
979 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1006 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 859 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
881 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
924 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
943 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
973 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1000 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 859 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
881 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
924 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
943 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
973 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1000 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 859 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
881 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
924 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
943 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
973 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1000 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 859 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
881 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
924 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
943 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
973 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1000 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 859 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
881 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
924 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
943 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
973 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1000 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 883 const TargetRegisterClass *QPRs, in producesFalseLanesZero() argument
905 if (!isRegInClass(MO, QPRs) && AllowScalars) in producesFalseLanesZero()
952 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID); in ValidateLiveOuts() local
973 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) in ValidateLiveOuts()
1016 if (!isRegInClass(MO, QPRs) || !MO.isDef()) in ValidateLiveOuts()
1045 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
|