/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/ |
H A D | sky2.c | 845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 951 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1056 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1063 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1333 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1334 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1359 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1688 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1690 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1691 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1786 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1789 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1818 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1832 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1895 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2073 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/net/ipxe/ipxe-2265a65/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/ |
H A D | sky2.c | 846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 848 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 849 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 952 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1057 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 1064 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); in sky2_rx_start() 1334 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down() 1335 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down() 1360 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down() [all …]
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H A D | skge.c | 1686 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset() 1687 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset() 1688 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset() 1689 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset() 1784 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop() 1787 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop() 1816 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down() 1830 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down() 1893 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame() 2069 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll() [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/Attributor/IPConstantProp/ |
H A D | openmp_parallel_for.ll | 89 ; NOT_TUNIT_NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 94 ; NOT_TUNIT_NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 95 ; NOT_TUNIT_NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double* 150 ; IS__TUNIT_NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 155 ; IS__TUNIT_NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 156 ; IS__TUNIT_NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double*
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/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/Attributor/IPConstantProp/ |
H A D | openmp_parallel_for.ll | 89 ; NOT_TUNIT_NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 94 ; NOT_TUNIT_NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 95 ; NOT_TUNIT_NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double* 150 ; IS__TUNIT_NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 155 ; IS__TUNIT_NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 156 ; IS__TUNIT_NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double*
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/ |
H A D | sky2.c | 1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 1082 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 1276 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 2052 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_tx_reset() 2076 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_hw_down() 2937 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); in sky2_rx_hung() 2938 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); in sky2_rx_hung() [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/ |
H A D | sky2.c | 1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 1082 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 1276 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 2052 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_tx_reset() 2076 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_hw_down() 2937 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); in sky2_rx_hung() 2938 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); in sky2_rx_hung() [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/ |
H A D | sky2.c | 1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset() 1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset() 1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset() 1082 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset() 1276 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum() 1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start() 2052 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_tx_reset() 2076 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_hw_down() 2937 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); in sky2_rx_hung() 2938 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); in sky2_rx_hung() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/Attributor/IPConstantProp/ |
H A D | openmp_parallel_for.ll | 94 ; IS________OPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 99 ; IS________OPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 100 ; IS________OPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double* 155 ; IS________NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 160 ; IS________NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 161 ; IS________NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double*
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/Attributor/IPConstantProp/ |
H A D | openmp_parallel_for.ll | 89 ; IS________OPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 94 ; IS________OPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 95 ; IS________OPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double* 150 ; IS________NPM-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8 155 ; IS________NPM-NEXT: store i64 4617315517961601024, i64* [[Q_ADDR]], align 8 156 ; IS________NPM-NEXT: [[CONV:%.*]] = bitcast i64* [[Q_ADDR]] to double*
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