/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_rcc_ex.h | 306 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 308 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 311 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 711 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 712 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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H A D | stm32l1xx_ll_bus.h | 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN in crc32c_cal()
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/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_rcc_ex.h | 306 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 308 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 311 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 711 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 712 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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H A D | stm32l1xx_ll_bus.h | 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
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/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_rcc_ex.h | 306 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 308 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 311 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 711 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 712 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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H A D | stm32l1xx_ll_bus.h | 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
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/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_hal_rcc_ex.h | 306 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 308 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 311 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 711 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 712 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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H A D | stm32l1xx_ll_bus.h | 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/ |
H A D | stm32f37x_rcc.h | 450 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/ |
H A D | stm32f37x_rcc.h | 450 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/inc/ |
H A D | stm32f30x_rcc.h | 542 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/ |
H A D | stm32f37x.h | 3937 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/ |
H A D | stm32f37x.h | 3937 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/ |
H A D | stm32f10x.h | 1780 …#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable … macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/ |
H A D | stm32f10x.h | 1780 …#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable … macro
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/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/ |
H A D | stm32l152xe.h | 4728 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
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/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/ |
H A D | stm32l152xe.h | 4728 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
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/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/ |
H A D | stm32l152xe.h | 4728 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
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/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/ |
H A D | stm32l152xe.h | 4728 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/ |
H A D | stm32f30x.h | 7446 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/ |
H A D | stm32f4xx.h | 8922 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) macro
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f4xx/ |
H A D | stm32f4xx.h | 8922 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) macro
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