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Searched refs:RCC_APB1ENR_TIM2EN (Results 1 – 25 of 88) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7m/stm32f1/
H A Dtimer.c20 #define RCC_APB1ENR_TIM2EN (1 << 0) macro
54 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); in timer_init()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7m/stm32f4/
H A Dtimer.c17 #define RCC_APB1ENR_TIM2EN (1 << 0) macro
51 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); in timer_init()
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
H A Dstm32l1xx_hal_rcc.h741 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
743 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
846 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1161 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1176 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
H A Dstm32l1xx_hal_rcc.h741 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
743 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
846 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1161 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1176 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
H A Dstm32l1xx_hal_rcc.h741 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
743 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
846 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1161 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1176 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN in crc32c_cal()
H A Dstm32l1xx_hal_rcc.h741 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
743 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
846 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1161 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1176 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_rcc.h438 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_rcc.h438 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/inc/
H A Dstm32f0xx_rcc.h433 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051, …
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c88 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c88 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c88 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c88 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/
H A Dclk_stm32f.c90 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c88 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c91 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c91 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c91 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c91 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c91 #define RCC_APB1ENR_TIM2EN BIT(0) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/inc/
H A Dstm32f30x_rcc.h535 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN

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