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Searched refs:RCC_APB2ENR_USART1EN (Results 1 – 25 of 40) sorted by relevance

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/dports/devel/tinygo/tinygo-0.14.1/src/machine/
H A Dmachine_stm32f407.go72 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
H A Dmachine_stm32f103xx.go96 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
H A Dstm32l1xx_hal_rcc.h917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
929 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1210 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1217 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
H A Dstm32l1xx_hal_rcc.h917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
929 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1210 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1217 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
H A Dstm32l1xx_hal_rcc.h917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
929 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1210 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1217 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_bus.h179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN in crc32c_cal()
H A Dstm32l1xx_hal_rcc.h917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
929 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1210 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1217 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_bus.h194 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
H A Dstm32g4xx_hal_rcc.h1118 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1120 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1194 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
1527 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
1558 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_rcc.h420 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A Dstm32f37x_rcc.h420 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/inc/
H A Dstm32f0xx_rcc.h417 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_hal_rcc.h1670 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1672 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1774 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
1797 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
1813 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
2723 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
2725 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
2827 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
3745 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
3747 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
[all …]
H A Dstm32h7xx_ll_bus.h232 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/inc/
H A Dstm32f30x_rcc.h518 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h3915 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h4161 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h3915 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h1742 #define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h1742 #define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable… macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h4696 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock en… macro
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h4696 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock en… macro

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