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Searched refs:RCC_CFGR_AHB_PSC_MASK (Results 1 – 25 of 64) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7m/stm32f1/
H A Dclock.c30 #define RCC_CFGR_AHB_PSC_MASK 0xF0 macro
176 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) in clock_get()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7m/stm32f4/
H A Dclock.c32 #define RCC_CFGR_AHB_PSC_MASK 0xF0 macro
189 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) in clock_get()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/
H A Dclk_stm32f.c40 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
341 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c38 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c41 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) macro
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()

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