Searched refs:RCC_CFGR_PLLMULL6 (Results 1 – 14 of 14) sorted by relevance
628 RCC_CFGR_PLLMULL6); in SetSysClockTo24()646 …->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); in SetSysClockTo24()650 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); in SetSysClockTo24()847 RCC_CFGR_PLLMULL6); in SetSysClockTo48()851 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); in SetSysClockTo48()
453 RCC_CFGR_PLLMULL6); in SetSysClockTo24()471 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); in SetSysClockTo24()678 RCC_CFGR_PLLMULL6); in SetSysClockTo48()682 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); in SetSysClockTo48()
1563 …#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6… macro1598 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ macro
321 … RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); in SetSysClock()
4032 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ macro
107 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
111 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
120 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
3784 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ macro
7305 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ macro