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Searched refs:RCC_DCKCFGRX_CK48MSEL (Results 1 – 25 of 62) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c70 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
185 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
188 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
198 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
269 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
272 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c70 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
185 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
188 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
198 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
269 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
272 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c70 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
185 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
188 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
198 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
269 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
272 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c70 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
185 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
188 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
198 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
269 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
272 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/
H A Dclk_stm32f.c72 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
187 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
190 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
200 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
203 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
271 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
274 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/
H A Dclk_stm32f.c70 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
185 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
188 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
198 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
269 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
272 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/
H A Dclk_stm32f.c73 #define RCC_DCKCFGRX_CK48MSEL BIT(27) macro
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); in configure_clocks()
272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()
275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; in stm32_clk_get_ck48msel()

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