| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/include/drivers/st/ |
| H A D | stm32mp1_rcc.h | 14 #define RCC_OCENCLRR U(0x10) macro
|
| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/include/drivers/st/ |
| H A D | stm32mp1_rcc.h | 14 #define RCC_OCENCLRR U(0x10) macro
|
| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/include/drivers/st/ |
| H A D | stm32mp1_rcc.h | 14 #define RCC_OCENCLRR U(0x10) macro
|
| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/include/drivers/st/ |
| H A D | stm32mp1_rcc.h | 14 #define RCC_OCENCLRR U(0x10) macro
|
| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/include/drivers/st/ |
| H A D | stm32mp1_rcc.h | 14 #define RCC_OCENCLRR U(0x10) macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 40 #define RCC_OCENCLRR 0x10 macro
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 40 #define RCC_OCENCLRR 0x10 macro
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 40 #define RCC_OCENCLRR 0x10 macro
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 40 #define RCC_OCENCLRR 0x10 macro
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 40 #define RCC_OCENCLRR 0x10 macro
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 49 #define RCC_OCENCLRR 0x10 macro
1206 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32mp1.c | 54 #define RCC_OCENCLRR 0x10 macro
1422 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
|