| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7m/stm32f4/ |
| H A D | clock.c | 29 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
136 | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) in configure_clocks()
179 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in clock_get()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 35 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
409 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 35 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
409 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 35 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
409 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 35 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
409 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/ |
| H A D | clk_stm32f.c | 37 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
179 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
411 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 35 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
409 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/ |
| H A D | clk_stm32f.c | 38 #define RCC_PLLCFGR_PLLP_SHIFT 16 macro
180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); in stm32_clk_get_rate()
|