/dports/multimedia/libva-intel-driver/intel-vaapi-driver-2.4.1/src/shaders/post_processing/gen5_6/Common/ |
H A D | RGBX_Save_YUV_Fix.asm | 77 …add (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 1)<0;4,4… 78 …add (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 1)<0;4,4… 79 …add (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 1)<0;4,4… 102 …add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:… 103 …add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:… 104 …add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:… 105 …add (4) REG2(r, nTEMP7, 0)<4>:w REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:… 106 …add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 2)<0;4,4>:… 107 …add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 2)<0;4,4>:… 108 …add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 2)<0;4,4>:… [all …]
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H A D | YUVX_Save_RGBX_Fix.asm | 108 …add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;… 109 …add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;… 110 …add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;… 111 …add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;… 112 …add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 2)<0… 113 …add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 2)<0… 114 …add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 2)<0… 115 …add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 2)<0… 143 …add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;… 144 …add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;… [all …]
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H A D | YUVX_Save_RGBX_Float.asm | 111 mov (8) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 118 mov (8) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 125 mov (8) REG2(r, nTEMP12, 16)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 128 mov (8) REG2(r, nTEMP12, 24)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 135 mov (8) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 138 mov (8) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub 156 mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 167 mov (8) REG2(r, nTEMP17, 0)<1>:d REG2(r, nTEMP16, 0)<0;8,1>:f 175 mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 222 mov (8) REG2(r, nTEMP17, 0)<1>:d REG2(r, nTEMP16, 0)<0;8,1>:f [all …]
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H A D | RGBX_Save_YUV_Float.asm | 95 mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 98 mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 101 mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 104 mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 107 mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f 125 mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f 126 mov (2) REG2(r, nTEMP12, 0)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w 128 mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f 129 mov (2) REG2(r, nTEMP12, 2)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w 131 mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f [all …]
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H A D | YUV_to_RGBX_Coef.asm | 61 mov (1) REG2(r, nTEMP0, 2):ud 0xFF9C012A:ud 62 mov (1) REG2(r, nTEMP0, 3):ud 0x0000FF30:ud 66 (-f0.1) mov (1) REG2(r, nTEMP0, 4):ud 0x0204012A:ud 67 (-f0.1) mov (1) REG2(r, nTEMP0, 5):ud 0x00000000:ud 68 ( f0.1) mov (1) REG2(r, nTEMP0, 0):ud 0x0204012A:ud 69 ( f0.1) mov (1) REG2(r, nTEMP0, 1):ud 0x00000000:ud 72 asr.sat (8) REG2(r,nTEMP0, 0)<1>:w REG2(r,nTEMP0, 0)<0;8,1>:w 1:w 73 asr.sat (4) REG2(r,nTEMP0,8)<1>:w REG2(r,nTEMP0,8)<0;4,1>:w 1:w 76 mov (1) REG2(r, nTEMP0, 6):ud 0x008080F0:ud 81 #define bYUV_OFF REG2(r,nTEMP0,24) [all …]
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H A D | RGBX_to_YUV_Coef.asm | 59 #define ubRGB_to_Y_Coef_Fix REG2(r, nTEMP0, 0) 60 #define bRGB_to_U_Coef_Fix REG2(r, nTEMP0, 4) 61 #define bRGB_to_V_Coef_Fix REG2(r, nTEMP0, 8) 64 (-f0.1) mov (1) REG2(r, nTEMP8, 0):f 0.114f // B coef 65 ( f0.1) mov (1) REG2(r, nTEMP8, 2):f 0.114f // R coef 66 mov (1) REG2(r, nTEMP8, 1):f 0.587f // G coef 67 (-f0.1) mov (1) REG2(r, nTEMP8, 2):f 0.299f // R coef 68 ( f0.1) mov (1) REG2(r, nTEMP8, 0):f 0.299f // B coef 89 #define fRGB_to_Y_Coef_Float REG2(r, nTEMP8, 0) 90 #define fRGB_to_U_Coef_Float REG2(r, nTEMP8, 4) [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/sparc/include/asm/ |
H A D | tsb.h | 161 andn REG2, 0x7, REG2; \ 166 andn REG2, 0x7, REG2; \ 171 sllx REG2, 32, REG2; \ 175 sllx REG2, 1, REG2; \ 178 andn REG2, 0x7, REG2; \ 182 sllx REG2, 32, REG2; \ 188 and VADDR, REG2, REG2; \ 193 andn REG2, 0x7, REG2; \ 221 sllx REG2, 1, REG2; \ 350 sllx REG2, 4, REG2; \ [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/sparc/include/asm/ |
H A D | tsb.h | 161 andn REG2, 0x7, REG2; \ 166 andn REG2, 0x7, REG2; \ 171 sllx REG2, 32, REG2; \ 175 sllx REG2, 1, REG2; \ 178 andn REG2, 0x7, REG2; \ 182 sllx REG2, 32, REG2; \ 188 and VADDR, REG2, REG2; \ 193 andn REG2, 0x7, REG2; \ 221 sllx REG2, 1, REG2; \ 350 sllx REG2, 4, REG2; \ [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/sparc/include/asm/ |
H A D | tsb.h | 161 andn REG2, 0x7, REG2; \ 166 andn REG2, 0x7, REG2; \ 171 sllx REG2, 32, REG2; \ 175 sllx REG2, 1, REG2; \ 178 andn REG2, 0x7, REG2; \ 182 sllx REG2, 32, REG2; \ 188 and VADDR, REG2, REG2; \ 193 andn REG2, 0x7, REG2; \ 221 sllx REG2, 1, REG2; \ 350 sllx REG2, 4, REG2; \ [all …]
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/dports/math/glm/glm-0.9.9.8/glm/gtc/ |
H A D | bitfield.inl | 24 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint16>(0x0F0F); 27 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint16>(0x3333); 30 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint16>(0x5555); 42 REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x00FF00FF); 45 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F); 48 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x33333333); 51 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint32>(0x55555555); 340 REG2 = ((REG2 >> 1) | REG2) & static_cast<uint16>(0x3333); 343 REG2 = ((REG2 >> 2) | REG2) & static_cast<uint16>(0x0F0F); 346 REG2 = ((REG2 >> 4) | REG2) & static_cast<uint16>(0x00FF); [all …]
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/dports/games/warzone2100/warzone2100/3rdparty/glm/glm/gtc/ |
H A D | bitfield.inl | 24 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint16>(0x0F0F); 27 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint16>(0x3333); 30 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint16>(0x5555); 42 REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x00FF00FF); 45 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F); 48 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x33333333); 51 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint32>(0x55555555); 340 REG2 = ((REG2 >> 1) | REG2) & static_cast<uint16>(0x3333); 343 REG2 = ((REG2 >> 2) | REG2) & static_cast<uint16>(0x0F0F); 346 REG2 = ((REG2 >> 4) | REG2) & static_cast<uint16>(0x00FF); [all …]
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/dports/devel/upp/upp/uppsrc/plugin/glm/gtc/ |
H A D | bitfield.inl | 24 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint16>(0x0F0F); 27 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint16>(0x3333); 30 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint16>(0x5555); 42 REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x00FF00FF); 45 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F); 48 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x33333333); 51 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint32>(0x55555555); 340 REG2 = ((REG2 >> 1) | REG2) & static_cast<uint16>(0x3333); 343 REG2 = ((REG2 >> 2) | REG2) & static_cast<uint16>(0x0F0F); 346 REG2 = ((REG2 >> 4) | REG2) & static_cast<uint16>(0x00FF); [all …]
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/dports/emulators/mess/mame-mame0226/3rdparty/glm/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555); 64 REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFFull); 89 REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF); 93 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F); [all …]
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/dports/audio/faust/faust-2.37.3/architecture/smartKeyboard/android/app/oboe/samples/RhythmGame/third_party/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555); 64 REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFFull); 89 REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF); 93 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F); [all …]
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/dports/graphics/libprojectm/projectm-3.1.12/vendor/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint16>(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint16>(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint16>(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint32>(0x55555555); 89 REG2 = ((REG2 << 16) | REG2) & static_cast<glm::uint32>(0xFF0000FFu); 93 REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x0F00F00Fu); 97 REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0xC30C30C3u); [all …]
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/dports/games/solarus/solarus-f43727b232b3ed13d98440a845e2a29e470e4f0d/libraries/win32/mingw32/include/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555); 64 REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFFull); 89 REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF); 93 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F); [all …]
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/dports/emulators/mame/mame-mame0226/3rdparty/glm/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555); 64 REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFFull); 89 REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF); 93 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F); [all …]
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/dports/graphics/nanort/nanort-b1feea8/examples/common/glm/glm/gtc/ |
H A D | bitfield.inl | 25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F); 28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333); 31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555); 43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF); 46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F); 49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333); 52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555); 64 REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFFull); 89 REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF); 93 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F); [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/ |
H A D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 103 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104 ; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 135 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] [all …]
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