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Searched refs:REG_MCRL (Results 1 – 12 of 12) sorted by relevance

/dports/emulators/mess/mame-mame0226/src/devices/machine/
H A D68340ser.cpp53 if ( (m_mcrh & REG_MCRH_STP) && offset != REG_MCRH && offset != REG_MCRL) in read()
65 case REG_MCRL: in read()
111 if ( (m_mcrh & REG_MCRH_STP) && offset != REG_MCRH && offset != REG_MCRL) in write()
126 case REG_MCRL: in write()
H A D68340ser.h43 REG_MCRL = 1, enumerator
/dports/emulators/mame/mame-mame0226/src/devices/machine/
H A D68340ser.cpp53 if ( (m_mcrh & REG_MCRH_STP) && offset != REG_MCRH && offset != REG_MCRL) in read()
65 case REG_MCRL: in read()
111 if ( (m_mcrh & REG_MCRH_STP) && offset != REG_MCRH && offset != REG_MCRL) in write()
126 case REG_MCRL: in write()
H A D68340ser.h43 REG_MCRL = 1, enumerator
/dports/devel/avr-gdb/gdb-7.3.1/sim/mn10300/
H A Dam33.igen33 return REG_MCRL;
1229 State.regs[REG_MCRL] = sum;
1258 State.regs[REG_MCRL] = sum;
1288 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCRL] = sum;
1335 State.regs[REG_MCRL] = sum;
1364 State.regs[REG_MCRL] = sum;
1396 State.regs[REG_MCRL] = sum;
1422 State.regs[REG_MCRL] = sum;
2244 State.regs[REG_MCRL] = sum;
[all …]
H A Dmn10300_sim.h133 #define REG_MCRL 27 macro
/dports/devel/gdb761/gdb-7.6.1/sim/mn10300/
H A Dam33.igen33 return REG_MCRL;
1229 State.regs[REG_MCRL] = sum;
1258 State.regs[REG_MCRL] = sum;
1288 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCRL] = sum;
1335 State.regs[REG_MCRL] = sum;
1364 State.regs[REG_MCRL] = sum;
1396 State.regs[REG_MCRL] = sum;
1422 State.regs[REG_MCRL] = sum;
2244 State.regs[REG_MCRL] = sum;
[all …]
H A Dmn10300_sim.h133 #define REG_MCRL 27 macro
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dam33.igen33 return REG_MCRL;
1229 State.regs[REG_MCRL] = sum;
1258 State.regs[REG_MCRL] = sum;
1288 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCRL] = sum;
1335 State.regs[REG_MCRL] = sum;
1364 State.regs[REG_MCRL] = sum;
1396 State.regs[REG_MCRL] = sum;
1422 State.regs[REG_MCRL] = sum;
2244 State.regs[REG_MCRL] = sum;
[all …]
H A Dmn10300_sim.h133 #define REG_MCRL 27 macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/mn10300/
H A Dam33.igen33 return REG_MCRL;
1229 State.regs[REG_MCRL] = sum;
1258 State.regs[REG_MCRL] = sum;
1288 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCRL] = sum;
1335 State.regs[REG_MCRL] = sum;
1364 State.regs[REG_MCRL] = sum;
1396 State.regs[REG_MCRL] = sum;
1422 State.regs[REG_MCRL] = sum;
2244 State.regs[REG_MCRL] = sum;
[all …]
H A Dmn10300_sim.h133 #define REG_MCRL 27 macro